JPS56153594A - Test method for storage device - Google Patents

Test method for storage device

Info

Publication number
JPS56153594A
JPS56153594A JP5724880A JP5724880A JPS56153594A JP S56153594 A JPS56153594 A JP S56153594A JP 5724880 A JP5724880 A JP 5724880A JP 5724880 A JP5724880 A JP 5724880A JP S56153594 A JPS56153594 A JP S56153594A
Authority
JP
Japan
Prior art keywords
address
counter
control circuit
data
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5724880A
Other languages
Japanese (ja)
Inventor
Yuichi Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5724880A priority Critical patent/JPS56153594A/en
Publication of JPS56153594A publication Critical patent/JPS56153594A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to test the address access time and address decoder function correctly, by repetitively making the data readout from the background address in ping-pong system while changing the reference address. CONSTITUTION:When the number of read times is set to the number of read time control circuit 1, the control circuit 4 gives the instruction signal to the mode control circuit 3 and the selector gate 6 and writes in the data D to all the addresses of the address counter 2-A. Next, the address (i) (reference address) is set to the address counter. Further, the data D is written in the address (i). The address i+1 is set to the counter 2-B to make n-time readout operation from the address i+1. Further, the readout of the address (i) of the counter 2-A is made and the counter 2-B is made to +1 and this is repeated. The circuit 4 receiving the signal in agreement with the content of the counters 2-A and 2-B from the comparison circuit 5-A, makes the counter 2-A by +1 and the entire processings are repeated.
JP5724880A 1980-04-28 1980-04-28 Test method for storage device Pending JPS56153594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5724880A JPS56153594A (en) 1980-04-28 1980-04-28 Test method for storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5724880A JPS56153594A (en) 1980-04-28 1980-04-28 Test method for storage device

Publications (1)

Publication Number Publication Date
JPS56153594A true JPS56153594A (en) 1981-11-27

Family

ID=13050220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5724880A Pending JPS56153594A (en) 1980-04-28 1980-04-28 Test method for storage device

Country Status (1)

Country Link
JP (1) JPS56153594A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031400A (en) * 1989-04-28 1991-01-08 Ncr Corp Method of testing lsi memory
JPH03180947A (en) * 1989-12-08 1991-08-06 Fujitsu Ltd Initial diagnostic system for ram
JP2008522334A (en) * 2004-11-26 2008-06-26 エヌエックスピー ビー ヴィ SRAM inspection method and SRAM inspection apparatus for detecting weak cells

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031400A (en) * 1989-04-28 1991-01-08 Ncr Corp Method of testing lsi memory
JPH03180947A (en) * 1989-12-08 1991-08-06 Fujitsu Ltd Initial diagnostic system for ram
JP2008522334A (en) * 2004-11-26 2008-06-26 エヌエックスピー ビー ヴィ SRAM inspection method and SRAM inspection apparatus for detecting weak cells

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