JPH03180947A - Initial diagnostic system for ram - Google Patents

Abstract

PURPOSE:To improve the reliability of a device by writing the data of a pattern different from a specific pattern only by the storage area of one address in a RAM, reading out addresses other than the written address and checking whether the data in the storage area is changed or not. CONSTITUTION:When an address storage area 231 in the cleared RAM (random access memory) 23 is selected by a RAM selecting signal 11 and data FF are written in the area 231, it may be that the storage data of the area 231 are FF and the storage data of residual storage areas 232 to 23n are 00. Thereby, the residual storage areas 232 to 23n are selected by RAM selection signals 12 to 1n and whether the read data are 00 or not is checked to decide the normality/abnormality of an address decoding circuit 22 in the RAM selecting signal (11) system. The normality/abnormality of the address decoding circuit 22 for all the addresses can be decided by similar processing. Thus, the reliability of the device can be improved.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a RAM initial diagnosis method for diagnosing whether or not RAM is operating normally, the present invention provides a method for performing quick and reliable RAM initial diagnosis, and improves the reliability of the device. In a method for diagnosing the normal operation of RAM used in microcomputer systems, after clearing the storage area of all addresses of the RAM with a specific pattern of data,
■Write data in a pattern different from the specific pattern only to the storage area of the address, read an address other than the written address to check whether the data in that storage area has changed, and write and read data to the RAM. This is done for each address, and serves as the bottom of the tank for diagnosing whether the address date circuit is normal or abnormal.

[Industrial Field of Application] The present invention provides R for diagnosing whether or not RAM operates normally.
Regarding AM initial diagnosis method.

RAM (Random Access Memory
) is widely used as a memory element in microcomputer systems, and it is important to check whether the RAM operates normally or not. Particularly in the case of a microcomputer system that remotely monitors/controls equipment (telemeter/telecontrol), ensuring reliability is an important issue because malfunctions have a serious impact, and therefore initial diagnosis of the RAM is important.

[Conventional technology]

Conventionally, the initial diagnosis of RAM is to check the total RAM 1iJ
A method is used in which a fixed pattern is written in the t area and it is checked whether the written contents can be read normally. However, with this method, the total RAM
Since the same data is written in the area, there is a problem in that abnormalities in the RAM address decoding circuit cannot be detected.

To explain this with reference to FIG.
00...0), if the address decoding circuit 22 is defective and the -1st bit A19 of the above address changes from 1 to 0, the address O
OO...0 (20 0's) RAM area 231
is accessed, and storage data 5A5A (16
The base number (data written in all RAM areas) is read out. In this case, the defect in the address decoding circuit 22 does not appear on the surface and the RAM area 2 at address 80000
The memory contents of 32 are 5^5^ as written, and there appears to be no abnormality.

In order to solve this problem, it is possible to set the data written to RAM to the same value as its address, and to issue an error if the RAM content and address do not match, but the number of bits of data (usually 8 or 16 bits) Since the number of address bits (usually 16 to 32 bits) is different from the address decoding circuit, if the data is 8 bits and the address is I6 bits, the same data will be written 28 times.
This method is not perfect because it cannot detect an abnormality in the second bit. This situation is shown in FIG. 4(b).

FIG. 4(b) shows an example in which the number of data bits is 16 and the number of address bits is 200, and the lower 16 bits of the address l-0... ...00 (binary number), and the lower 1 is stored in the area 233 of the address 0OOOH (hexadecimal number).
6 bits 0...01 (binary number), address 0
In the area 234 of 0002 (hexadecimal number), its lower 16 bits 0...10 (binary number) are written as check data.

As you can see, if the address decoding circuit 22 is defective and the A19 bit changes from 1 to 0, the processor 21 will
R of 0002 (100...10 in hexadecimal, binary)
When the A M eM area 235 is accessed, the RAM area 234 at address 00002 (hexadecimal number) is actually accessed and the stored data O...10 is read out, but the stored data in the area 235 is also read out. Since the result is 10, it is as planned and the check result appears to be normal. In addition, this method requires checking the entire RAM area, and the diagnostic speed becomes an issue when it is desired to shorten the initial startup time of the system.

[Problem to be solved by the invention]

In this way, in conventional RAM initial diagnosis methods, it is not possible to detect address decoder defects if the same data is written to all addresses, and if the same data is written to each address as the address, the number of address bits is greater than the number of data bits. If there are more cases, the same data will be written repeatedly, making it impossible to reliably detect address decoder defects.Also, in any of the above methods, it is necessary to read all addresses, which increases the time required for diagnosis. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to improve the disadvantages, provide a method for performing quick and reliable initial diagnosis of RAM, and contribute to improving the reliability of the device.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the present invention. This microcomputer system includes a processor (CPLI) 21, a ROM (Read Only) that stores programs, and
Memory) 26, RAM 23, address decoding circuit 22, address bus 24, and data bus 25
The present invention provides an address decoding circuit 2 for this RAM.
This provides a means for confirming the normality of operation of No. 2.

In the present invention, for this diagnosis, after clearing the storage area of all addresses of the RAM 23 with data of a specific pattern,
Data of a pattern different from the specific pattern is written only in the storage area of the address, and an address other than the written address is read to check whether the data in the storage area has changed.

This writing and reading is performed for each address of the RAM to check whether the address decoding circuit is normal or not.

The address to be written or read consists of multiple binary bits, with any bit set to 1 and the remaining bits set to 0.
This can be done for each address.

Some RAMs have areas that cannot be cleared.

For such RAM, as shown in Figure 1 (c), the area where the bit of an address consisting of multiple bits is 1 or later, in the example shown in the figure, 1000 to 3FFF (hexadecimal numbers, the same applies to others) is cleared. Possible, area 0 where the bit (2 bits) is O
000 to 0FFF cannot be cleared, and the above-mentioned clearing, writing, and reading processing is performed only for the clearable areas 1000 to 3FFF.

[Effect]

Through the above processing, it is possible to diagnose whether the address decoding circuit is normal or abnormal.

That is, when the operation of the address decoding circuit 22 is normal,
Storage area 231 at an address in RAM 23 after clearing
If FF is selected by the RAM selection signal 11 and data FF is written, the data stored in the storage area 231 of the RAM 23 should be FF, and the data stored in the remaining storage areas 232 to 23n should be 00. Therefore, the remaining storage areas 232-23
By selecting n with the RAM selection signal 12~in and checking whether the read data is OO, R
It is found that the address decode circuit 22 of the AM selection signal 11 system is normal/abnormal, and by performing the same process for each address, it is found that the address decode circuit 22 for all addresses is normal/abnormal.

A certain bit of the address becomes 0 or l (0 or l
), there should be double selection, and in the read processor, all 00s should appear, but FFs will also appear. This abnormality can be checked using the above process.

Since the normality/abnormality of the address decoding circuit can be checked for each bit of the address, the above writing/succession can be performed for all address bits with only I set to 1 and the rest set to 0, and all bits set to O. . This makes it possible to significantly reduce the time required for diagnosis compared to all address writing/successive writing. For example, the RAM address area is oo
ooo~7F'FFF, writing/continuing all addresses is 80000 x 80000 (both 16
(base number) RAM access is required, but if you want to write/read something where only one bit is 1 and the rest are 0, or something where all bits are 0, it will be necessary to access the RAM 20x20 times (all bits are 1
(0 base number) number of RAM accesses are required.

0 The address bit is fixed to O, l, which occurs when the signal line of the bit is short-circuited to the ground or power supply line.
In addition to this, there is a short between lines.

If there is a non-clearable area in the RAM, by distinguishing it by 0.1 of a certain bit of the address, the diagnostic method of the present invention can be easily applied to the clearable area except for the non-clearable area. For example, the write/continuation address is simply incremented from the start address 0000, and this is logically ORed with the start address 1000 of the clearable area to make it the actual access address, thereby clearing only the clearable area. , can be written/continued.

〔Example〕

An embodiment of the present invention is shown in FIGS. 2 and 3. In Figure 2,
At first, in the step of clearing the entire RAM area, the address of the RAM to be accessed is set to the starting address 00000 (
Hexadecimal number, this comment is omitted as it is for the following),
The address of the RAM to be accessed after that is the final address +
The contents of each RAM address (
In this example, 1 word of 8 bits) is set to a predetermined value, 00 in this example.
Then, add 1 to the RAM address and repeat this operation until the address reaches 80,000. The contents of each address in the RAM will now be all 0.

Next, proceed to the step of checking the RAM address decoder (■). If so, proceed as follows. That is, first, the check destination address (address where data is written) is set to ooooo, and 8-bit data (in this example, FF) is written to this address. Next, it is checked whether the contents of addresses other than the check source have changed (2), and this is done as follows.

That is, the check destination address (read address) is set as the check destination address, and the check destination address - check destination address, until the check destination address reaches 80000.
If this is YES, check starts) Check destination address is updated; if No (checking in progress) check destination address contents -00? If this is YES, the check destination address is updated; if NO, it is RAM address decoder abnormality 2 (2), so an alarm is issued and the system is stopped.

In this way, when the check destination address is updated and the content is checked to see if it is OO until it reaches 80000, the contents of the check destination address are returned to 00, which is the same as the contents of other addresses (2), the check destination address is updated, and the process returns to the beginning. In other words, set the contents of the check destination address to FF and check whether the contents other than the check source have changed.
shall be. The check destination address is updated to 80000 while performing the processing to check the contents, and if there is no abnormality in the contents, the RAM address decoder is normal (2), and the diagnosis is proceeded.

If you simply increment the check destination address, RA
All addresses of M (excluding the check destination address) must be read, which increases the time required.

It is sufficient to check each bit of the address in the address decoder, so in Fig. 3, 0000
0.00001.00002.00004.・・・・・・
. . . This is done by sequentially setting each bit of the binary address to l. In this way, for 20 bits 3 address A19...AO,
) If the source address is A19-A1=OAO=1, then A19-A2. AO=0. If A1=1, 18 times...
I ended up with a series of...

FIG. 3 shows the diagnosis procedure when a part of the RAM area is not cleared. Data that should not be erased may be written in the RAM, and FIG. 3 deals with this case. In this view, the area where a certain bit Ai or bit Aj of the address is 1 is 0100...0 (the first 0 is A4, the next l is Aj, the following 0 is Ai, the bit lower than Aj; in this view Binary number) ~ 111...l
can be cleared, this area OOO where Ai and Aj are 0
...0 to 0011...1 cannot be cleared. In Figure 3, Ai = A1B, Aj = Al 7, and the area where A1B = A17 = O cannot be cleared, and Al
Areas where at least one of B or A17 is 1 can be cleared.

In Figure 3, the RAM area is first cleared (■), but this is an area that can be cleared from 20000 to 711 F F F
I'll go there 4 times.

Next, check the RAM address decoder■
However, at this time, the forced on-pit position is set to 40000.

This means setting A1B = 1, and writing/outputting the area that can be cleared one after another.
If 1B is fixed to 1, it is not possible to tell whether this A18 bit of the address decoder is normal or abnormal. Therefore, the forced on-pit position is set to 20000, that is, A17=1, and the normality/abnormality of the A18 bit is also checked using these two types of diagnosis.

Checking the RAM address decoder (2) sets the check destination address to ooooo, writes address 8FF which is the logical sum of this and the forced on pit position 40000, and checks whether or not the contents other than the check source have changed. If it changes, the RAM address decoder is abnormal.■
Therefore, an alarm is issued, the system is stopped, and if there is no change, the check destination address is updated (2), the contents of the write address are returned to 00, and the write address is updated. In this way, if the content up to the final value 80000 is OO as expected, it means that the RAM address decoder is normal (2), and the diagnosis ends.

The present invention can also be used in combination with conventional systems such as those shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, it becomes possible to quickly check for abnormalities in the RAM address decoding circuit at the time of initial diagnosis, which has not been done in the past, thereby making it possible to improve the reliability of the device and It greatly contributes to improving the reliability of computer systems.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIGS. 2 and 3 are explanatory diagrams of embodiments 1 and 2 of the present invention, and FIG. 4 is an explanatory diagram of a conventional system. In FIG. 1, 21 is a processor of the microcomputer system, 23 is a RAM, and 22 is its address decoding circuit. Applicant Shitsu stock% formula% comparison

Claims (1)

[Claims] 1. RAM used in microcomputer system
In the method of diagnosing the normal operation of the RAM (23
) storage area for all addresses (231, 232,...)
After clearing with a specific pattern of data, write data in a pattern different from the specific pattern to only one address storage area, read an address other than the written address, and check whether the data in that storage area has changed. This RAM initial diagnosis method is characterized by checking whether the address date circuit is normal or abnormal by checking the writing and reading for each address of the RAM. 2. Writing and reading are performed for each address in which only one arbitrary bit of an address consisting of a plurality of bits is 1 and the remaining bits are 0.
AM initial diagnosis method. 3. In a method for diagnosing the normal operation of RAM, which is used in microcomputer systems and some areas cannot be cleared, the address range that can be cleared is when a certain bit of the address is 1.
, the address range that cannot be cleared is the corresponding bit (
2 bit) is set to 0, and after clearing a storage area in a clearable address range where the bit is 1 with data of a specific pattern, writing data of a pattern different from the specific pattern only to the storage area of 1 address, Read addresses other than the written address to check whether the data in that storage area has changed, and perform this writing and reading for each address in the RAM clearable address range to check whether the address date circuit is normal or not. A RAM initial diagnosis method characterized by diagnosing abnormalities.