JPS5730019A - Information processing device - Google Patents
Information processing deviceInfo
- Publication number
- JPS5730019A JPS5730019A JP10481980A JP10481980A JPS5730019A JP S5730019 A JPS5730019 A JP S5730019A JP 10481980 A JP10481980 A JP 10481980A JP 10481980 A JP10481980 A JP 10481980A JP S5730019 A JPS5730019 A JP S5730019A
- Authority
- JP
- Japan
- Prior art keywords
- address
- high speed
- signal
- written
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Digital Computer Display Output (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To increase average processing speed, by using memories which are possible for high speed operation in the relation with an input and output device. CONSTITUTION:A decoder DEC decodes an address given from a controller which controls DMA, and when the high-speed mode is selected, clocks CLs 1, 2 are made to high speed and written in a high speed side memory with a read/write switching signal R/W and a memory data register MDR. When the accessing is finished once, a signal is outputted to an information MS to produce the next address and the next information is written in an F-RAM. When a readout is made with DMA system and display is made on e.g. a cathode ray tube CRT, the signal R/W is switched and a memory MEM is selected through the provision of an address and operation is made to provided the next address.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10481980A JPS5730019A (en) | 1980-07-30 | 1980-07-30 | Information processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10481980A JPS5730019A (en) | 1980-07-30 | 1980-07-30 | Information processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5730019A true JPS5730019A (en) | 1982-02-18 |
Family
ID=14391004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10481980A Pending JPS5730019A (en) | 1980-07-30 | 1980-07-30 | Information processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5730019A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59157734A (en) * | 1983-02-25 | 1984-09-07 | Canon Inc | Data transfer system |
-
1980
- 1980-07-30 JP JP10481980A patent/JPS5730019A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59157734A (en) * | 1983-02-25 | 1984-09-07 | Canon Inc | Data transfer system |
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