JPH031400A - Method of testing lsi memory - Google Patents

Abstract

PURPOSE: To make it possible to check a memory error occurring independently of a write-in address in a short time by checking the effect when write-in is performed on a block after an IC memory is divided into plural blocks, all for every block. CONSTITUTION: The memory is divided into plural blocks by an initialization means 2 and a characteristic detection means 4 according to elements common to physical constitution such as arrangement and wiring, etc., of respective cells. Then, the effects given to other blocks when one block is accessed are checked for every block related to the whole blocks by a mutual blocks error check means 10 for checking the mutual blocks effects such as an effect that the write-in operation on the specified block affects other blocks, or the like, with divided with each block as unit. Thus, performing write-in or read-out operation to a specified address, when the error occurs in the address different to that, an error is found out by a test in a relatively short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory testing method for a highly integrated chip-based memory.

[Prior art]

Conventional memory test methods include (1) a method in which 1# or "0" data is written to all addresses and then read and checked, (2) a march pattern test method, and (3) There is a gearropping test method.

Here, the march pattern test method is to write data ``0'' to all addresses, and write ``0#'' starting from the first address.
After reading and confirming, the sequence of writing 7”-data “1” to the first address is repeated until the last address, and “1” is written to the final address.Next, read and confirm the “1” at the final address. , and then writing "0" there, repeating the sequence from the last address to the first address. Gearloping test method is a test method in which data "0" is written at all addresses.
” and then write data “1” to the first address.Next, read and confirm “O” at the first address other than the first address, then read and confirm “1” at the first address.Furthermore, read and confirm all other addresses other than the first address. After confirming that the address is 0'', data ``On'' is written to the first address. This is a test method in which the same sequence is repeated until the final address.

[Problem that the invention seeks to solve]

Recently, with the increasing integration of memo IJ-IC, conventional IC
The following points, which were not so much of a problem with memory, have become a problem.

(b) When a write or read operation is performed to a specific address, an error may occur at a different address.

(o) The above error (b) occurs only when writing or reading operations are performed consecutively to a plurality of specific addresses.

On the other hand, the test methods according to the prior art techniques (1) and (2) cannot detect the above-mentioned errors (A) and (0). In addition, the method according to prior art (3) cannot detect errors, and since highly integrated memories have a large capacity, this method has the problem that it takes a long time to test the memory.

[Purpose of the invention]

An object of the present invention is to provide a memory testing method that effectively solves these problems in conventional testing methods and can detect the above-mentioned errors (A) and (O) in a relatively short test time. .

[Means for solving problems]

The present invention provides that the above memory error (A), (I:I) is
Focusing on the fact that this often occurs due to the physical structure of C memory (memory cell and line arrangement, etc.), Divide into a plurality of blocks, and (1) Check the effect that accessing one block has on other blocks for each block, using each divided block as one unit.

The above objective was achieved by conducting a memory test using this method.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing means for implementing the test method according to the present invention, and FIG. 2 is a diagram showing the basic flow of the test method according to the present invention.

Figures 3 (A) and (B) explain the arrangement of each cell and the state of charge charged in each cell when a memory chip is divided into blocks based on row addresses or column addresses. This is a diagram of the end. In FIG. 1, reference numeral 2 denotes initial setting means, which performs block division settings, test data and back data settings. Reference numeral 4 denotes a cell characteristic detecting means, which checks the cell characteristic of each cell in the memory chip when setting back data, etc. 6i
-1: Test sequence control means, memory
Take overall control of your testing. 8 is a back data write/read means that tests the basic read/write operations of the memory chip and also fills the entire memory with predetermined back data to prepare for the next test. Reference numeral 10 denotes inter-block error checking means for checking the influence between blocks, such as the influence that a write operation on a particular block has on other blocks. 12 is a back data writing means 8 or an inter-block error checking means 10;
This is an error processing means that displays an error such as an error address when it is confirmed that an error has occurred. 1
4 is an IC memory (memory to be tested) to be subjected to a memory test.

The operation of each part shown in FIG. 1 will be explained according to the basic operation flow shown in FIG. 2.

Initial setting is performed by the initial setting means 2 and the cell characteristic detecting means 4, and consists of (1) designation of block division, (2) setting of hack data, and (3) setting of test data.

(1) Block division designation Block division, which is one unit of memory testing, is designated based on common elements in the physical configuration of the memory under test 14.

Examples are shown in FIGS. 3(A) and 3(B).

FIGS. 3A and 3B show the memory 14 to be tested according to the physical arrangement of cells. Figure 3 (A
) This shows a case where blocks are divided based on the hello address, and in this case, cells common to the row address lines in the horizontal rows constitute one block. Figure 3 (B) shows a case where blocks are divided based on column addresses, and there is one cell common to column address lines in a column.
It will form a block.

(2) Setting of back data The read/write test using back data is a basic operation test of the entire memory, and at the same time, it is a test to fill the entire memory with the same data for the subsequent memory test. It is. Therefore, all bits of the back data are basically set to "11" or "0".

Filling the entire memory with the same data in this way is
This is because by adjusting the potentials charged in each cell to a constant level in advance, it is possible to more efficiently test the influence of charged charges between blocks in a subsequent test.

However, in this regard, the following problems arise due to differences in the structure of cells of memory chips.

In other words, some memory cells use a potential of "--A" (hereinafter referred to as "H'") to represent a logic level (for example, 1") or a low (hereinafter referred to as "L"). Depending on the type of memory chip used, both of these two types of cells may be used in a mixed manner within the same chip.

Therefore, simply set the back data to logic “1” or “0”.
Even if you write to all addresses in the memory with ``, it may not be possible to align the charge potentials of each cell to the same potential.For example, in FIG. 3(A), at row address 1
It is assumed that the block 2 shown by is composed of cells that express logic "1" with potential °L1, and all the cells of the other blocks are composed of cells that express logic "1" with "H". shall be. If you write back data as "1" to the entire memory chip with this configuration,
Only the cells of block 2 will be in the potential "L" state. For a chip with such a configuration, the charge potential of the entire memory can be set to "H" by setting the back data only at the address corresponding to block 2 to logic "O#" and setting the others to "1". ” can be arranged.

From the above explanation, by charging a specific block with a charge opposite to that of other blocks, K, which examines the degree of influence between blocks caused by the charge, is calculated by charging each cell constituting the memory chip. You should understand that it is necessary to know the characteristics of

The characteristics of each cell in the memory chip can be known by the cell characteristics detection means 4 (FIG. 1).

The cell characteristic detection means 4 determines the cell characteristics by reading each memory cell immediately after power is turned on. In addition, immediately after the power is turned on, the cells are not charged with charge, so the logic level read immediately after the power is turned on corresponds to the "L" potential of each cell. For example, in FIG. 3(A), if only block 2 is "L" and represents logic "1", the data read immediately after power is turned on is block 2.
only the block becomes logic “1”, all other blocks become logic “0”
”. Therefore, for example, if you want to put the entire memory cell in the “H” state, the cell characteristic detection means 4
Data opposite to the logical level read out (Figure 3 (A))
), only block 2 is set to logic “0” and the others are set to “1”.
”) as the backing data.

(3) Setting of test data Test data refers to data written to a specific block in an inter-block error test. Test data can be freely set according to the purpose of the test. For example, as shown in Figure 3 (A) and (B), if you want to perform an operation test in which only a specific block (block 2) is charged with a charge opposite to that of other blocks, All you have to do is set the data as test data. Also, if necessary, “101
The bits may be alternately inverted such as 010...10#.

As explained above, (1) block division specification, (2)
Specifically, the setting of hack data and (3) designation of test data can be performed as follows. First, in accordance with the basic structure of various IC memories, block division/P-turn, back data, test data, and turns are stored in advance according to the type of each IC. Then, during the initial setup, the operator
Select and input 5 turns of memory according to the type of C memory or the chip configuration of IC memory. 1. Alternatively, the operator may input all data each time initial settings are made.

Step 22) Write the back data set in the initial settings to the entire memory, then read all addresses and compare the read data with the back data to check whether a write error has occurred.

The inter-block error test is a test that checks the effect of accessing one block on other blocks.

After writing the back data and checking it,
Test data is written to the first block. After that, in order to check whether an error has occurred in other blocks due to the write operation, write a block (hereinafter referred to as a "read block") other than the block to which the test data was written (hereinafter referred to as a "write block"). “) is read and compared with the back data. Next, in order to check whether an error has occurred in the write block due to the read operation of the read block, the write block is read every time one of the read blocks is read and its contents are used as test data. be compared.

For one write operation to the first block, the above read comparison test is performed for all blocks.

When this is completed, the write block number is updated, the next write is performed on the second block, and the same read comparison test is repeated.

By repeating the above write and read operations, when the test data has been written to all blocks and the read comparison test for each write operation has been completed, the blocks can be compared with each other using one back data and test data. The error test ends. If necessary, it is also possible to change the back data and test data and further perform an inter-block error test.

Next, an embodiment of the present invention will be described in more detail with reference to FIG.

FIG. 4 is a flow chart showing a more specific embodiment of the memory testing method of the present invention. In this example,
It is assumed that each memory cell stores the logic "l#" at "H'".First, initialization means 2 performs a puncture.
The data is set to "0", the test data to 11", the write block number WB=1, and the read block number RB=2 (step 30).

Next, the puncture data is read through the sequence control means 6.
Write back data “0” to all blocks by writing means 8
is written (step 32). When writing is completed, all data is read out and it is checked whether puncture data has been written correctly (Stella F32.34).
). If it is an error, the process jumps to step f58 for error processing, and an error display etc. is performed. If there is no error, the sequence control means 6 controls the inter-block error testing means 10 to perform the following test.

First, the block with write block number WB (currently WB=1
Therefore, test data "1" is written in block 1) (step 36). Thereafter, the block with the read block number RB (RB=2, therefore block 2) is read out, and the read data is compared with the back data to confirm whether an error has occurred (Step 7'38.40). By reading and comparing block 2 in this way,
It is possible to check whether an error has occurred in the data of block 2 due to the write operation to block 1.

Next, the write block WB=1 is read out, and the read data is compared with the test data to check whether an error has occurred (steps f42, f44). This allows checking for write errors in the write block and checking the write block (block 2) accompanying the read operation of block 2.
) can be checked.

In either case, if an error occurs, error processing is performed (steps 40, 42, and 58).

If no error has occurred, read block number “R”
B" is added by "1' (step 46). If the added result is equal to the write block number WB, 1'' is further added (step 46).

Next, RB is compared with the last block number LB, and if RB is less than the last block number LB, step 38
The block RB readout and the block 1 readout test are repeated as before (step 48.3).
8, 40.44.46).

The fact that "RB" exceeds the final block number LB indicates that the read test for all blocks for the write operation of block 1 has been completed. Therefore, in that case, the same 0 as the back data is sent to block WB=1.
” (step 49), add “1” to WB to update the write block and write (step 5).
0).

Next, "WB" is compared with the final block number LB.

Now, WB=2 and LB has not been exceeded yet, so test data "1" is written to block WB=2 (steps f52, 36).

Thereafter, the read comparison test is repeated in the same manner as in the case of writing to block 1 (steps 38 to 48), and all effects of writing to block WB on other blocks are checked. The above operations are performed for all blocks while updating the write block WB, and when WB becomes larger than the final block LB, the process goes from step 52 to step f54, where it is confirmed whether or not the test for all test data has been completed. Ru. If not, the puncture
The initial settings such as data and test data are changed (step 56), and the same test is repeated (steps 32 to 54).

The memory test ends when the test data of all types is completed (Stella f54).

In this embodiment, writing to the updated write block WB is performed using a normal write operation (step 50.52.3).
Although 6) is shown, the block WB may be written to by other commands that require a higher speed operation, such as a MOVE command.

Furthermore, the test of the IC memory according to the present invention may be performed at the final product test stage of a product using the IC memory (for example, an ECR, etc.).

For example, if the IC memory test of the present invention is performed while performing a heat resistance test of the final product (ECR, etc.), the memory test can be performed under more severe conditions and the test time can be significantly saved.

〔Effect of the invention〕

As explained above, the present invention divides an IC memory into a plurality of blocks in accordance with the structural characteristics of the IC so that the combinations are likely to cause errors, and then By checking all effects on blocks in block units, it is now possible to check memory errors that occur at addresses unrelated to write addresses in a short time.

In addition, since it is possible to determine the test data and test data after checking the characteristics of the cells in the IC memory in advance, it is possible to conduct more rigorous tests that take into account the effects of charges between cells or on wiring, etc. can now be done in specific blocks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing means for implementing the test method of the present invention. FIG. 2 is a flow chart showing the basic operation of the test method of the present invention. FIGS. 3A and 3B are diagrams showing the relationship between blocks of an IC memory divided according to the physical configuration and Charso charges, respectively. FIG. 4 is a flowchart showing one embodiment of the present invention in more detail. 2... Initial setting means, 4... Cell characteristic detection means, 6
...Test sequence control means, 8...Puncture
Data reading/writing means, 10... Inter-block error/
Checking means, 12...Error processing means, 14...Memory to be tested Application agent Isao Saito (A) 1st CB)

Claims (1)

[Scope of Claims] (a) Divide the LSI memory into a plurality of blocks in association with common elements in the physical configuration such as the arrangement and wiring of each cell, and (b) Divide predetermined back data into the IC memory. By writing to all addresses, all cells of the IC memory are charged with the same charge, and (c) to examine the effect on other blocks when writing access to one of the divided blocks is performed. (d) writing test data into one block and reading out the contents of all other blocks block by block each time the writing is performed; and comparing the read data with the back data; If the read data is different from the back data, perform error processing; (e) If the read data is equal to the back data, write the test data in the next block sequentially; An IC memory testing method consisting of each process, which performs each process of (d).