JPS6127000A - Inspection method of ram - Google Patents

Inspection method of ram

Info

Publication number
JPS6127000A
JPS6127000A JP14840884A JP14840884A JPS6127000A JP S6127000 A JPS6127000 A JP S6127000A JP 14840884 A JP14840884 A JP 14840884A JP 14840884 A JP14840884 A JP 14840884A JP S6127000 A JPS6127000 A JP S6127000A
Authority
JP
Japan
Prior art keywords
data
address
ram
read
ram3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14840884A
Other languages
Japanese (ja)
Other versions
JPH0346920B2 (en
Inventor
Shinichi Iizuka
真一 飯塚
Katsuyasu Fujii
克泰 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14840884A priority Critical patent/JPS6127000A/en
Publication of JPS6127000A publication Critical patent/JPS6127000A/en
Publication of JPH0346920B2 publication Critical patent/JPH0346920B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To decide a RAM to be functioning normally when an address to be confirmed is sequentially added by one and when it exceeds an address of a RAM3 by writing/reading data in accordance with each address of the RAM and simultaneously detecting whether or not data of other addresses are destructed. CONSTITUTION:When the indication is given for inspecting a start of write/read of a RAM3, a micro processor 1 reads a program out of a ROM2 to start checking the RAM3. First of all, a specific data, for instance, a hexadecimal 55H is written in all the addresses of the RAM3. After that, an address to be confirmed is specified for trial reading of the data. When the read-out data is not 55H, the RAM3 is decided to be abnormal. Whereas the read-out data is 55H, another specific data, for instance, a hexadeciman AAH is written in the same address. The data is read by specifying the address to which the AAH is written. When the read-out data is AAH, all the addresses are sequentially specified for data reading. When the entire read-out data is 55H as it is, an address is added by one, and if is exceeds the address of the RAM3, the RAM is decided to be normal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はRAMに対してデータの書込み/ ice出し
を行う装置に係り、特にRAMの検査方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for writing data to/outputting data to/from a RAM, and particularly relates to a method for inspecting a RAM.

最近のオフィスオートメーシジン(OA)ia器はマイ
クロプロセッサを内蔵し、RAMにデータを格納して処
理するようになってきた。そしてこれ等のOA機器では
、コストを干けるためRAM及び書込み/続出し回路に
、娯り横用手段を持たないものが多い。
Recent office automation (OA) IA devices have built-in microprocessors and have come to store and process data in RAM. In order to reduce costs, many of these OA devices do not have a means for recreational use in the RAM and write/continue output circuits.

しかしOA機器の商性能化に伴い処理するデータ量が増
え、R、A Mの容量も増大している。従ってRAM機
能の信頼性が重要視されるようになってきた。そこでこ
れ等の機器の中りこは電源投入時又はオペレータの診断
時に、RAM機能のチェックを行うものも少なくない。
However, as the commercial performance of OA equipment increases, the amount of data to be processed increases, and the R and AM capacities also increase. Therefore, the reliability of RAM functions has become more important. Therefore, in many of these devices, the RAM function is checked when the power is turned on or when an operator diagnoses the device.

このRAM機能チェック時には、書込み/続出し回路を
含み確実な機能チェックが、簡単ムこ実施出来ることが
必要である。
When checking the RAM function, it is necessary to be able to easily perform a reliable function check including the write/continuation circuit.

〔従来の技術〕[Conventional technology]

RAM機能のチ、lZ7りの方法としては、まず或アド
レスにデータ(55H)を書込んた後に、本当に書込ま
れているかとうか読出して確認し、次に同しアドレスに
データ〔ΔA H)を書込み、これを読出して確認する
。この動作を総てのアドレス空間に対して行うのが一般
的である。
The method for RAM function is to first write data (55H) to a certain address, read it to check whether it has actually been written, and then write data [ΔA H) to the same address. Write and read and confirm. This operation is generally performed for all address spaces.

即ち01 (11(l ]を書込んで読出し、次に同じ
アドレスに101010を書込んで読出すことにより、
データに誤りか発住しているかどうかでRAMの55i
當検出を行う。
That is, by writing and reading 01 (11(l), and then writing and reading 101010 to the same address,
55i of RAM depending on whether there is an error in the data or not.
Perform the detection.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の方法によりRAM機能のチェックを行うと、例え
ばRAMのデコード回路が故障し、アドレス信号が正し
く出ていなくて、指定したアドレスにデータが書込まれ
ないにも拘わらず、チェック結果が良となることがある
If you check the RAM function using the above method, for example, the check result may be good even though the RAM decoding circuit has failed and the address signal is not output correctly and no data is written to the specified address. It may happen.

即ちアドレス信号の最下位ビットが常に1″となってし
まったとすると、(xxxO)番地と(xxxl)番地
のどちらを指定しても、データは(xxxl)番地に書
込まれる。しかし上記方法では番地の確認をしていない
ため、障害か検出されず良となってしまうという問題か
ある。  ′〔問題点を解決するための手段〕 上記問題点は、RAMに対してデータの書込みと読出し
を行う装置において、RAMの総′このアドレスに特定
のデータAを書込む第1の工程と、任意のアドレスを指
定してデータを読出し、そのデータが前記特定のデータ
Aかどうかをf#認する第2の工程と、特定のデータA
が確認された時に、前記アドレスを指定して前記データ
八とは異なる特定のデータBを書込み、その後そのアド
レスを指定してデータを読出し、そのデータか前記特定
のデータBかどうかを確認する第3のL稈と、特定のデ
ータBが確認された時に、前記アドレスを除く総てのア
ドレスを順次指定してデータを読出し−そのデータが前
記特定のデータAかどうかをl認する第4の工程とを含
み、RAMの総てのアドレスに対して前記第2の工程か
ら第4の工程を行うようにした、本発明によるRAMの
検査方法によって解決される。
In other words, if the least significant bit of the address signal is always 1'', data will be written to address (xxxl) regardless of whether address (xxxO) or address (xxxl) is specified.However, with the above method, Because the address is not checked, there is a problem that a failure is not detected and becomes a failure.' [Measures to solve the problem] The above problem is caused by the failure when writing and reading data to and from RAM. In a device that performs the following steps, the first step is to write specific data A to this address in the total RAM, read out the data by specifying an arbitrary address, and check whether the data is the specific data A or not. Second process and specific data A
is confirmed, specifying the address and writing specific data B different from the data 8, then specifying the address and reading the data, and confirming whether the data is the specific data B or not. When the L culm of No. 3 and the specific data B are confirmed, all the addresses except the above address are sequentially designated and the data is read out.The fourth step is to check whether the data is the specific data A. The problem is solved by the RAM inspection method according to the present invention, which includes steps and performs the second to fourth steps for all addresses of the RAM.

〔作用〕[Effect]

即ちRAMの各アドレス毎にデータの書込み/読出しを
ITうと共に、他のアドレスのデータが破壊されでいな
いかどうかを検出する。
That is, data is written/read for each address of the RAM, and it is detected whether data at other addresses has been destroyed.

〔実施例〕〔Example〕

第1図ば本発明の一実施例を示す回路のブロック図でプ
リンタの回路例を示し、第2図は第1図の動作を説明す
るフローチャートである。
FIG. 1 is a circuit block diagram showing an example of a printer circuit according to an embodiment of the present invention, and FIG. 2 is a flowchart explaining the operation of FIG. 1.

マイクロプロセッサ1はROM2に格納されているプロ
グラムを読出して動作する。インタフェース制御回″路
4からは印字データ等が入る。マイクロプロセッサ1は
該印字データを一旦RAM3に書込む。
The microprocessor 1 reads a program stored in the ROM 2 and operates. Print data etc. are input from the interface control circuit 4. The microprocessor 1 temporarily writes the print data into the RAM 3.

RAM3に書込まれた印字データはマイクロプロセッサ
1により読出され、文字コードであれば文字発生回路7
から該当する文字パターンが読出されて印字ヘット制御
回路IOに送出される。印字ヘッド制御回路10に送出
された文字パターンは印字ヘット11により印字される
The print data written in the RAM 3 is read out by the microprocessor 1, and if it is a character code, it is read out by the character generation circuit 7.
The corresponding character pattern is read out from the printhead control circuit IO and sent to the print head control circuit IO. The character pattern sent to the print head control circuit 10 is printed by the print head 11.

この時マイクロプロセッサ1は同時にスペース制御回路
8を制御して、スペースモータ9を駆動し、印字ヘット
11を運搬するキャリッジのスペース動作を行わせる。
At this time, the microprocessor 1 simultaneously controls the space control circuit 8 to drive the space motor 9 to cause the carriage carrying the print head 11 to perform a space motion.

マイクロプロセッサIJvよRA M 3から読出した
印字データに改行指定があると、改行制fal1回路5
を制御して改行モータ6を駆動し、紙送りを行わせる。
If the print data read from RAM 3 by the microprocessor IJv has a line feed specification, the line feed system fal1 circuit 5
is controlled to drive the line feed motor 6 to feed the paper.

オペレータパネル13から入力ポート12を経てマイク
ロプロセッサ1に、第2図に示す如くRAM3の書込み
/読出し検査開始の指軍かあると、マイクロプロセッサ
1ばROM2からプログラムを読出して、RAM3のチ
ェックを開始する。
When the microprocessor 1 receives a command from the operator panel 13 via the input port 12 to start checking the writing/reading of the RAM 3 as shown in FIG. 2, the microprocessor 1 reads the program from the ROM 2 and starts checking the RAM 3. do.

まずRAM3の全アドレスに特定のデータ例えば16進
の(55H)を書込む。その後確認すべきアドレスを指
定してそのデータを続出してみる。
First, specific data, such as hexadecimal (55H), is written to all addresses in the RAM 3. After that, specify the address to be checked and try outputting that data one after another.

ここで読出したデータか(55H)でなけれはRAM3
の異常と判定するが、読出したデータが〔55H〕であ
れば同一アトレスに別の特定のデータ例えば16進の〔
AAH〕を書込む。
If it is not the data read here (55H), it is RAM3.
However, if the read data is [55H], other specific data, such as hexadecimal [
AAH].

前記で〔△ΔH)を書込んだアドレスを指定してデータ
を読出してみる。ここで読出したデータが〔A△1]〕
でなげれはRAM3の異常と判定するか、読出したデー
タが〔ΔAH)であれば、総てのアドレスを順次指定し
てデータの読出しを行う。
Specify the address where [ΔΔH] was written above and read the data. The data read here is [A△1]]
If the deviation is determined to be an abnormality in the RAM 3, or if the read data is [ΔAH], all addresses are sequentially designated and the data is read.

そのデータか(55H)でないものかあればRAM3の
異常と判定するが、読出したデータが総て(55H)の
ままならば、確認するアドレスを+1する。
If any of the data is not (55H), it is determined that the RAM 3 is abnormal, but if all the read data remains (55H), the address to be checked is incremented by 1.

確認すべきアドレスを順次+1して、RA M 3のア
ドレスを越えなければ、上記の動作を繰り返し、RA 
M 3のアドレスを越えたならば、RAM3は+に常と
判定して終了する。
Increase the address to be checked by +1 one by one, and if it does not exceed the address of RAM 3, repeat the above operation, and RA
If the address of M3 is exceeded, it is determined that RAM3 is always positive and the process ends.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明は書込み/続出し回路を含み
総ての)?AM機能を容易にチェックすることが出来る
As explained above, the present invention includes a write/sequence circuit and all)? AM function can be easily checked.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路のブロック図・ 第2図は第1図の動作を説明するフローチャートである
。 1はマイクロプロセッサ、 2はROM、  、   3はRAM。 4ばインクフェース制御回路、 5は改行制御回路、  6は改行モータ、7は文字発生
回路、 8はスペース制御回路、9はスペースモータ、
10は印字へノド制御回路、11ば印字ヘッド、  1
2は入力ポート、13はオペレータパネルである。
FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention. FIG. 2 is a flowchart explaining the operation of FIG. 1. 1 is a microprocessor, 2 is a ROM, and 3 is a RAM. 4 is an ink face control circuit, 5 is a line feed control circuit, 6 is a line feed motor, 7 is a character generation circuit, 8 is a space control circuit, 9 is a space motor,
10 is a printing gutter control circuit; 11 is a print head; 1
2 is an input port, and 13 is an operator panel.

Claims (1)

【特許請求の範囲】[Claims]  RAMに対してデータの書込みと読出しを行う装置に
おいて、RAMの総てのアドレスに特定のデータAを書
込む第1の工程と、任意のアドレスを指定してデータを
読出し、そのデータが前記特定のデータAかどうかを確
認する第2の工程と、特定のデータAが確認された時に
、前記アドレスを指定して前記データAとは異なる特定
のデータBを書込み、その後そのアドレスを指定してデ
ータを読出し、そのデータが前記特定のデータBかどう
かを確認する第3の工程と、特定のデータBが確認され
た時に、前記アドレスを除く総てのアドレスを順次指定
してデータを読出し、そのデータが前記特定のデータA
かどうかを確認する第4の工程とを含み、RAMの総て
のアドレスに対して前記第2の工程から第4の工程を行
うことを特徴とするRAMの検査方法。
In a device that writes and reads data to and from a RAM, the first step is to write specific data A to all addresses in the RAM, and the first step is to read data by specifying an arbitrary address, and the data is read from the specified address. a second step of confirming whether or not data A is specified; and when specific data A is confirmed, specifying the address and writing specific data B different from the data A, and then specifying the address. a third step of reading data and confirming whether the data is the specific data B, and when the specific data B is confirmed, sequentially specifying all addresses except the address and reading the data; That data is the specific data A
A method for inspecting a RAM, characterized in that the second step to the fourth step are performed for all addresses of the RAM.
JP14840884A 1984-07-17 1984-07-17 Inspection method of ram Granted JPS6127000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14840884A JPS6127000A (en) 1984-07-17 1984-07-17 Inspection method of ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14840884A JPS6127000A (en) 1984-07-17 1984-07-17 Inspection method of ram

Publications (2)

Publication Number Publication Date
JPS6127000A true JPS6127000A (en) 1986-02-06
JPH0346920B2 JPH0346920B2 (en) 1991-07-17

Family

ID=15452118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14840884A Granted JPS6127000A (en) 1984-07-17 1984-07-17 Inspection method of ram

Country Status (1)

Country Link
JP (1) JPS6127000A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273691A (en) * 1986-05-22 1987-11-27 Canon Inc Electronic apparatus
JPH031400A (en) * 1989-04-28 1991-01-08 Ncr Corp Method of testing lsi memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56101699A (en) * 1980-01-14 1981-08-14 Meidensha Electric Mfg Co Ltd Ram fault diagnostic system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56101699A (en) * 1980-01-14 1981-08-14 Meidensha Electric Mfg Co Ltd Ram fault diagnostic system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273691A (en) * 1986-05-22 1987-11-27 Canon Inc Electronic apparatus
JPH031400A (en) * 1989-04-28 1991-01-08 Ncr Corp Method of testing lsi memory

Also Published As

Publication number Publication date
JPH0346920B2 (en) 1991-07-17

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