JPH08138391A - Flash memory control system - Google Patents

Abstract

PURPOSE: To obtain a flash memory control system in which abnormality can be analyzed effectively while enhancing the maintainability. CONSTITUTION: The flash memory control system comprises a block erasure flag 5 being set at the time of block erasure of a flash memory, and a flag set circuit 6 for controlling the flag wherein the content can be confirmed by means of a MPU 1 through a status register 7. Since the MPU 1 can decides whether the block of a flash memory for which an error is detected is already written in, a decision can be made whether a detected error represents an abnormality in the memory itself.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory control system having an area for storing error check bits in a computer system having a flash memory as a storage device.

[0002]

2. Description of the Related Art A flash memory does not require a dedicated jig for writing / erasing its contents, and is a read-only memory (Write Only Memory) capable of electrically writing / erasing contents while mounted on a printed circuit board. ROM). Conventional EEPROM (Electrically Erasable and Program
Since the structure of the memory cell is simpler than that of a mable read only memory), higher integration / capacity can be achieved. For this reason, it has been widely used as a substitute for a floppy disk or a hard disk in a small computer system.

An example of a computer system using the flash memory 3 as a storage device is shown in FIG. The device shown in this figure executes a process of reading a program or data from a flash memory, and at the same time a microprocessor unit (hereinafter referred to as MPU) 1 for writing to the flash memory, checks the check bit when reading the data from the flash memory. It is composed of an error check circuit 2 for detecting whether the data is proper, a memory write control circuit 12 for creating a write timing when writing data to the flash memory of the MPU, and an address decoder. Currently, most of the flash memories on the market are divided into a plurality of blocks, and the contents of each block are erased collectively.
This is a method of writing data to an erased block, and erasing / writing of data (or check bit) is executed by inputting a command to the memory by the program of the MPU. When performing block erasing / writing on the flash memory, the MPU outputs the address of the space where the memory is mapped on the address bus and the first parameter of the data write command. When the address decoder 4 recognizes that the flash memory is selected by the signal on the address bus, it outputs the access signal 8 to the memory write control circuit to notify the start of access.
Upon receiving the access signal, the memory write control circuit
If the MPU write signal 9 from U is confirmed and it is recognized that the writing is to the flash memory, the memory write signal 10 is output. Then, after the writing is executed, the memory writing control circuit stops the output of the memory writing signal, and notifies the MPU of the completion of one access by the bus response signal 11. By repeating these operations and performing a necessary command write operation to the flash memory, the block erase / write operation is completed.

The data written by the command input from the MPU and the check bit are read together when the data is read from the memory and collated by the error check circuit.

[0005]

The flash memory is
As the manufacturing process becomes finer / higher density and larger in capacity, it is likely to be affected by various external disturbances such as external radiation, magnetic field, and electric field, and it is expected that the frequency of soft errors will increase. Therefore, in order to minimize the system down due to soft error and build a highly reliable computer system, parity check and ECC are required.
The addition of a memory check mechanism such as (Error Check and Correct) will become indispensable. In these memory check mechanisms, a check bit is provided separately from a data storage area, a check bit is automatically generated according to the content of data on the data bus, and the check bit is written together with the data. Then, when reading the memory, the data part and the check bit part are collated, and if the contents are incompatible, it is reported to the MPU as a data error.

Most of the erasing of the flash memory is executed in block units of several tens to several hundred bytes. When writing data, once erasing one block, the block is erased. Data must be written to the entire area. Therefore, if the flash memory is configured with a check bit, if data is mistakenly erased and then data is read from a block that has not been written, a mismatch between the data section and the check bit will occur It will be judged as an error. In such a case, it is very difficult to judge whether the data error is caused by an erroneous memory access or the memory error is actually caused.

[0007]

In order to solve the above problems, the present invention makes it possible to easily identify the cause of an error when an error is detected when reading data from a flash memory. Improve reliability / maintenance.

FIG. 1 shows a flash memory management system according to the present invention. According to the present invention, reading / writing of data with respect to the flash memory 3 is executed by the MPU 1. The control unit for reading data from the flash memory reads the contents read from the address decoder 4, which detects the flash memory access, and the data storage unit 31,
The error check circuit 2 is configured to check the presence or absence of data abnormality by collating with the contents read from the check code storage unit 32. On the other hand, management of the erased / unwritten state of the flash memory is performed by the block erase flag 5, the flag set circuit 6, and the status register 7.

When erasing a block of the flash memory, the MPU executes it by writing a block erasing command and a parameter designating a block to be erased in the flash memory. The address decoder that has detected the memory access specifies the memory access to the flash memory by the access signal 8. When the memory write control circuit 12 determines that the write access is made by the memory access signal and the MPU write signal 9 from the MPU, the memory write control circuit outputs the memory write signal 10 to execute the write. Then, at the end of one memory access cycle,
It responds to the MPU with a bus response signal 11. On this occasion,
The flag set circuit is an access signal and an MPU from the MPU.
Depending on the content of the write signal and the data to be written,
When it is recognized that this memory access is block erasure, the state shifts to the block erase flag set standby state.
Then, when the block to be erased is designated subsequently, the block designated to be erased is set in the block erase flag added to each block. The contents of the block erasing flag can be recognized by the MPU through the status register, so that which block is currently being erased can be known. MPU
After erasing the memory, after writing the data to the block, when the writing is completed for the entire one block, the flag is cleared through the status register.

By providing this mechanism, even if a data read access to a block is erroneously executed and a memory error occurs while the data write to the block is not completed, the MPU In error processing, it is possible to identify whether the error is caused by a processing error of the MPU or a memory error that has actually occurred, so it is effective during error analysis, and this makes memory maintenance easier. Can be improved.

[0011]

In the present invention, the MPU 1 executes control such as data read / write and block erase with respect to the flash memory 3. When reading data from the flash memory, the MPU outputs the specified address in the flash memory and starts access. M
Address decoder 4 which receives the specified address from PU
When it is determined that the addressing is the flash memory, the data is read from the data storage unit 31 and the check code storage unit 32, the error check circuit 2 collates the data, and the presence or absence of data abnormality is checked. As a result, if there is a mismatch between the data and the check code, it is reported to the MPU as a data abnormality. When data is read, the block erase flag 5, the flag set circuit 6, and the status register 7 manage the state of whether or not the contents of the flash memory of the block are valid.

Block erase of flash memory is performed by MP
U is executed by executing a protocol such as a block erasing command for the flash memory and a parameter for designating a block to be erased in the flash memory. The address decoder that has detected the memory access specifies the memory access to the flash memory by the access signal 8. When the memory write control circuit 12 determines that the memory access signal is the write access by the memory access signal and the MPU write signal 9 from the MPU, the memory write control circuit outputs the memory write signal 10 to execute the write. Then, at the end of one memory access cycle, the bus response signal 11 is returned to the MPU. At this time, if the flag set circuit recognizes that the write memory access is block erase based on the access signal, the MPU write signal from the MPU, and the content of the data to be written, it shifts to the block erase flag set standby state and the flag is set. It is ready to set. After this standby state, when the information designating the block to be erased is subsequently designated, among the block erase flags added for each block according to this information, the flag set corresponding to the block to be erased is set. To do. The contents of the block erasing flag can be recognized by the MPU through the status register, and thereby, which block is currently being erased can be known. MPU is
After erasing a block of memory, write the data and check code to that block according to the write protocol of the flash memory, and when the writing is completed for the entire erased block, clear the block erase flag through the status register. Execute and make the data in that block valid (written).

If the MPU performs a read access to a block which has not been written yet after the erasure, a data error occurs because a mismatch of the contents occurs between the data and the check code. However, by providing this mechanism, the cause of the data error detection at the time of data error detection may be the result of erroneously executing the data read access to the block while the data write to the block is not completed. (MPU
This is effective at the time of error analysis because it is possible to identify in the MPU memory error processing whether it is due to a software error) or a true memory error (hardware error). As a result, the maintainability of the memory can be improved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a flash memory writing system according to the present invention will be described with reference to the block diagram of FIG.

In this embodiment, the MPU 1 reads a program or data stored in the flash memory 3 and uses the contents to perform processing. The erasing / writing of the contents of the flash memory is executed by the MPU when the program version is updated. In writing, the data storage unit 31 and the check code storage unit 32 of the flash memory are performed independently. The address decoder that has detected the memory access specifies the memory access to the flash memory by the access signal 8. This memory access signal and MPU from MPU
When the memory write control circuit 12 determines from the write signal 9 that it is a write access, the memory write control circuit outputs a memory write signal and executes writing. When writing to the data storage unit, by designating the data storage unit write mode by the write control register 13, the write signal of the flash memory is output to the write signal 15 only to the data storage unit. In this state, a protocol such as writing a write command is executed, and the writing is executed. Similarly, when writing to the check code storage unit, the check code storage unit write mode is specified by the write control register, and then the check code calculated by the MPU is written, so that the check code storage unit is written. The write signal 16 is output only to. The bus response signal 11 is responded to for one memory access cycle.

When reading data from the flash memory, the MPU outputs the specified address in the flash memory and starts access. When the address decoder 4 receives the designated address from the MPU and determines that the address designation is the flash memory, it simultaneously reads the contents written in the above procedure from the data storage unit and the check code storage unit, and reads the contents. The error check circuit 2 collates and checks whether there is a data abnormality. As a result, when there is a mismatch between the data and the check code, the data error signal 14 is responded together with the bus response signal, and is reported to the MPU as a data abnormality.

Block erasing of flash memory is performed by MP
U is executed by executing a protocol such as a block erasing command for the flash memory and a parameter for designating a block to be erased in the flash memory. The write operation is the same as when writing data, but by specifying the block erase mode with the write control register,
Since the memory write signal is output to both the data storage unit and the check code storage unit, both the data and the check code can be erased at the same time. When the flag set circuit 6 recognizes the block erase by the write control register, it shifts to the block erase flag set standby state and waits for the number of output of the memory write signal. After the standby state, when the number of times of the memory write signal indicates the state of writing the parameter for designating the erase block, the block erase flag 5 added to each block according to this information.
The flag corresponding to the block to be erased is set. If the block erase flag is set, its contents can be read by the MPU through the status register 7 (the erased block bit indicates 1), which block is currently being erased. You can know what is going on. After erasing the block of the memory, the MPU writes the data and the check code to the block according to the write protocol of the flash memory, and when the writing is completed to the block, writes 1 to the corresponding bit in the status register. As a result, the contents of the block erase flag are cleared, and the data in the block is valid (written) at that point.

If, after erasing, the MPU performs a read access to a block in which writing has not been completed, a data error signal is output because a content mismatch occurs between the data and the check code. , Data error is detected. However, in the error processing of the MPU, by collating the contents of the status register with the address of the flash memory where the error is detected,
Whether it is the result of erroneously executing a data read access to the block when data writing is not completed (MPU software error) or a true memory error (hardware error) Can be identified in the memory error processing of the MPU.

[0019]

According to the present invention, the MPU can recognize whether the accessed flash memory block has already been written. Therefore, it is possible to determine whether the detected error is an abnormality of the memory itself. Because,
This is effective for abnormality analysis and can improve maintainability.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system using a flash memory according to the present invention.

FIG. 2 is a block diagram of a computer system using a flash memory according to the related art.

FIG. 3 is a block diagram of a computer system using a flash memory according to an embodiment.

[Explanation of symbols]

1 ... MPU, 2 ... Error check circuit, 3 ... Flash memory, 4 ... Address decoder, 5 ... Block erasing flag, 6 ... Flag setting circuit, 7 ... Status register,
8 ... Access signal, 9 ... MPU write signal, 10 ... Memory write signal, 11 ... Bus response signal, 12 ... Memory write control circuit.

Claims (1)

[Claims] 1. A flash memory that is an electrically writable / electrically erasable read-only memory, in which the contents of the memory are divided into a plurality of blocks, and each block can be erased / written to A microprocessor unit for reading and writing data from and to the flash memory, and an address decoder for detecting flash memory access from the microprocessor unit when the microprocessor unit writes / reads to / from the flash memory. In the microcomputer system described above, a check for storing a data area for storing a program or data in the configuration of the flash memory, and a check code determined according to the contents stored in the data area Each block has a block erase flag indicating that the block has been erased and the data stored in the flash memory is invalid when the block is erased from the flash memory. By providing a block erasing register mechanism whose contents can be recognized by the microprocessor unit, the state of the flash memory can be managed and the error check function by the check code can be effectively used. A flash memory control method characterized by the above.