JPH11297099A - Semiconductor integrated circuit device and test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to select either 0 or 1 state on bloc about a plurality of cells in a unit and write them by having a function for writing data en bloc in a plurality of memory cells at a test mode and capable of selecting either 0 or 1 state for the data. SOLUTION: At a test mode, a logically reverse level to the usual state is given to a signal 7 for going to a test mode state, resulting in a test mode state. Signals inputted from 4, 5, 6 are enabled. In this embodiment data to be written en bloc is determined according to the logic level of 6. In this sequence of operation the write is made for 1/4 of the capacity of all memory elements. The logic levels of word line select signal at a test mode of 4 and bit line select signal of 5 are changed to complete the data write of all the memory elements after total 4 cycles of operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology of a semiconductor integrated circuit device having a rewritable storage element.

[0002]

2. Description of the Related Art Conventionally, in order to test a rewritable storage element, an address of the storage element is sequentially changed and data is written to each storage element. Some storage elements have a circuit for initializing all data to one state and all data to zero state in batch erasure or dynamic stress application test.

[0003]

However, in the conventional method, a method of sequentially writing data is generally used, and there is a problem that the test time increases when the capacity of the storage element increases. Also, when performing erasing and writing all at once, the data is all in the 0 state or all in the 1 state, and it cannot be arbitrarily selected. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device having a function of arbitrarily selecting either a zero state or a one state for a plurality of cells in a certain unit and writing the same, and a test method therefor.

[0004]

In order to solve this problem, a semiconductor integrated circuit device according to the present invention comprises: a) a semiconductor integrated circuit device having a rewritable storage element; b) a plurality of memory cells in a test mode. Data writing can be performed collectively, and c) the data can be selected from either a 0 state or a 1 state.

Further, the test method is as follows: d) The semiconductor integrated circuit device according to claim 1, e) by performing batch writing of data in a test mode, thereby fixing data in memory cells and preventing interference between memory cells. Data writing for performing an electrical characteristic test is performed in a short time.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a diagram in which the present invention is applied to a semiconductor integrated circuit device including a storage element having eight word lines, eight bit lines, and eight data input terminals. In FIG. 1, reference numerals 1, 2, and 3 denote circuit blocks for realizing the present invention. 4 is a signal for selecting a word line in the test mode. An even or odd word line is selected according to the logic level of this signal. Reference numeral 5 denotes a signal for selecting a bit line in the test mode. Bit lines in even or odd rows are selected according to the logic level of this signal. Reference numeral 6 denotes a signal for selecting whether data to be written in the test mode is set to the 0 state or the 1 state. 7 is a signal for entering the test mode state. In the test mode, a level logically opposite to the normal state is input to 7. As a result, a test mode state is established, and signals input from 4, 5, and 6 become valid. At this time, with respect to word lines, every other word line is selected by one selection circuit according to the logic level of the signal of four. As for the bit lines, bit lines in every other column are selected by two selection circuits in accordance with the logic level of the signal of five. Although data may be input from a normal data input terminal, in this example, data to be subjected to batch writing is determined according to the logical level of 6. In this series of operations, writing of a quarter of the capacity of all storage elements is performed. All data written during writing of this quarter capacity is the same data. By changing the logic levels of the word line selection signal in the test mode 4 and the bit line selection signal 5, the data writing to all the storage elements is completed by a total of four operations. Therefore, the greater the capacity of the storage element, the greater the effect on the test time. When a circuit as in the embodiment of the present invention is used, even if the capacity of the storage element changes, the steps of this operation do not change. Regarding the test method, first, writing is performed with the word line selection signal in test mode 4 set to 0 state, the bit line selection signal in 5 test mode set to 0 state, and the data selection signal 6 set to 0 state. Next, the bit line selection signal of 5 is set to 1 state, and the data selection signal of 6 is set to 1 state, and writing is performed. Further, the word line selection signal in test mode 4 is set to 1 state, the bit line selection signal in test mode 5 is set to 0 state, and the data selection signal 6 is set to 1 state to perform writing. Finally, the bit line selection signal of 5 is set to 1 state, and the data selection signal of 6 is set to 0 state to perform writing. With the above operation, the writing of the cell checker pattern can be realized.

The embodiment of the present invention is merely an example, and the same test can be easily performed with the same circuit even when the number of word lines, the number of bit lines, and the number of data are changed.

Furthermore, in the embodiment of the present invention, a circuit for selecting half of the word lines and bit lines is used. However, if the selection circuit is changed, the same test can be easily performed by changing the selection division method. It is.

[0010]

As described above, according to the present invention, a complicated input test pattern for sequentially writing data to a storage element is not required, and as a result, a test time for executing them is required. Test of the storage element can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Circuit block for realizing the present invention (logic circuit for selecting word line) 2 Circuit block for realizing the present invention (logic circuit for selecting bit line) 3 Circuit block (data for realizing the present invention) 4 A word line select signal in test mode 5 A bit line select signal in test mode 6 A data select signal in test mode 7 Test signal

Claims (2)

[Claims] A) a semiconductor integrated circuit device having a rewritable storage element; b) data can be written to a plurality of memory cells at a time in a test mode; c) a state of 0 for the data; Alternatively, a semiconductor integrated circuit device having a function in which any one of the states can be arbitrarily selected. 2. The semiconductor integrated circuit device according to claim 1, wherein: b) performing batch write of data in a test mode, thereby fixing data in memory cells and testing electrical characteristics for interference between memory cells. Test method characterized by performing data writing for a short period of time.