JPS56140595A - Multilevel rom - Google Patents

Multilevel rom

Info

Publication number
JPS56140595A
JPS56140595A JP4181580A JP4181580A JPS56140595A JP S56140595 A JPS56140595 A JP S56140595A JP 4181580 A JP4181580 A JP 4181580A JP 4181580 A JP4181580 A JP 4181580A JP S56140595 A JPS56140595 A JP S56140595A
Authority
JP
Japan
Prior art keywords
word lines
transistor
selection
line
cell group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4181580A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP4181580A priority Critical patent/JPS56140595A/en
Publication of JPS56140595A publication Critical patent/JPS56140595A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states

Abstract

PURPOSE:To make it possible to input data consisting of not less than two bits to one transistor by composing a cell group of a high-voltage power source, word lines, a selection line, cell transistors, and a selection transistor. CONSTITUTION:Part of address input 36 is decoded by address decoder 37, and output 38 consists of word lines and a selection line. In memory array 39, word lines, a selection line and a power line run and bit line 40 runs lengthwise. Memory array 39 is composed of cell group 71 as a unit. Cell group 71 consists of high- voltage power source 47, word lines 48-51, selection line 52, bit line 59, cell transistors 61-64, and selection transistor 65. In this constitution, data consisting of not less than two bits can be inputted to one transistor.
JP4181580A 1980-03-31 1980-03-31 Multilevel rom Pending JPS56140595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4181580A JPS56140595A (en) 1980-03-31 1980-03-31 Multilevel rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4181580A JPS56140595A (en) 1980-03-31 1980-03-31 Multilevel rom

Publications (1)

Publication Number Publication Date
JPS56140595A true JPS56140595A (en) 1981-11-02

Family

ID=12618797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4181580A Pending JPS56140595A (en) 1980-03-31 1980-03-31 Multilevel rom

Country Status (1)

Country Link
JP (1) JPS56140595A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103093A2 (en) * 1982-09-13 1984-03-21 Kabushiki Kaisha Toshiba Multi-bit-per-cell read only memory circuit
US4902190A (en) * 1987-09-14 1990-02-20 Cascade Corporation Fork positioning attachment for lift trucks
US6672823B2 (en) 2001-09-11 2004-01-06 Cascade Corporation Fork positioner for facilitating replacement of forks on lift trucks
WO2004003926A3 (en) * 2002-06-27 2004-03-25 Matrix Semiconductor Inc Low-cost, serially-connected, multi-level mask-programmable read-only memory
US7909563B2 (en) 2004-11-30 2011-03-22 Cascade Corporation Fork positioner
US8403618B2 (en) 2004-11-30 2013-03-26 Cascade Corporation Lift truck load handler

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103093A2 (en) * 1982-09-13 1984-03-21 Kabushiki Kaisha Toshiba Multi-bit-per-cell read only memory circuit
US4902190A (en) * 1987-09-14 1990-02-20 Cascade Corporation Fork positioning attachment for lift trucks
US6672823B2 (en) 2001-09-11 2004-01-06 Cascade Corporation Fork positioner for facilitating replacement of forks on lift trucks
US7008167B2 (en) 2001-09-11 2006-03-07 Cascade Corporation Fork positioner for facilitating replacement of forks on lift trucks
WO2004003926A3 (en) * 2002-06-27 2004-03-25 Matrix Semiconductor Inc Low-cost, serially-connected, multi-level mask-programmable read-only memory
US7909563B2 (en) 2004-11-30 2011-03-22 Cascade Corporation Fork positioner
US8403618B2 (en) 2004-11-30 2013-03-26 Cascade Corporation Lift truck load handler

Similar Documents

Publication Publication Date Title
JPS5771574A (en) Siemconductor memory circuit
JPS563499A (en) Semiconductor memory device
JPS57105884A (en) Cmos memory decoder circuit
TW368754B (en) An adjustable threshold voltage conversion circuit
JPS56140595A (en) Multilevel rom
JPS5641579A (en) Address selector
JPS5694576A (en) Word decoder circuit
TW344823B (en) Address decoder
KR870009388A (en) Static Semiconductor Memory
JPS5619584A (en) Semiconductor memory
KR900002310A (en) Decoding method of semiconductor memory device and semiconductor memory device employing the method
JPS54119847A (en) Memory unit
JPS56159897A (en) Read-only memory
TW335494B (en) The decode method of high density ROM array
JPS5514588A (en) Semiconductor dynamic memory unit
JPS5552593A (en) Memory unit
KR850008561A (en) Semiconductor Lead Only Memory Device
JPS5477544A (en) Logic circuit
JPS5782288A (en) Dynamic memory
JPS57176590A (en) Memory device
JPS5616991A (en) Semicondcutor memory unit
TW279987B (en) The word line driving circuit of mask ROM
JPS5271141A (en) Word line driving circuit
JPS56111191A (en) Read only memory device
JPS5782297A (en) Semiconductor storage device