JPS56137748A - Mutliplexing circuit - Google Patents

Mutliplexing circuit

Info

Publication number
JPS56137748A
JPS56137748A JP3969380A JP3969380A JPS56137748A JP S56137748 A JPS56137748 A JP S56137748A JP 3969380 A JP3969380 A JP 3969380A JP 3969380 A JP3969380 A JP 3969380A JP S56137748 A JPS56137748 A JP S56137748A
Authority
JP
Japan
Prior art keywords
parallel
series
bit
registers
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3969380A
Other languages
Japanese (ja)
Inventor
Tadashi Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3969380A priority Critical patent/JPS56137748A/en
Publication of JPS56137748A publication Critical patent/JPS56137748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To decrease the number of circuits and signal lines between elements by providing bit-parallel signal lines only between series-parallel converting shift registers and parallel-series converting shift registers, and series-parallel converting shift registers and input latch registers. CONSTITUTION:Input highways HW1-HW6 through which bit-serial signals are transmitted are connected to input terminals of series-parallel converting shift registers 71-76 provided correspondingly. Registers 71-76 load one-channel signals as bit-parallel signals to input terminals D1-D8 of correspondingly provided parallel- series converting shift registers 81-86 where bit-parallel signals are inputted. Then, as registers 81-86 are put into operation with high-speed clock signals, a high-speed bit-serial signal is outputted from parallel-series converting shift register 86 in the final-stage.
JP3969380A 1980-03-28 1980-03-28 Mutliplexing circuit Pending JPS56137748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3969380A JPS56137748A (en) 1980-03-28 1980-03-28 Mutliplexing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3969380A JPS56137748A (en) 1980-03-28 1980-03-28 Mutliplexing circuit

Publications (1)

Publication Number Publication Date
JPS56137748A true JPS56137748A (en) 1981-10-27

Family

ID=12560113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3969380A Pending JPS56137748A (en) 1980-03-28 1980-03-28 Mutliplexing circuit

Country Status (1)

Country Link
JP (1) JPS56137748A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007829A1 (en) * 1989-01-09 1990-07-12 Fujitsu Limited Digital signal multiplexer and separator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990007829A1 (en) * 1989-01-09 1990-07-12 Fujitsu Limited Digital signal multiplexer and separator

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