JPS56138350A - Bidirectional and undirectional conversion circuit - Google Patents

Bidirectional and undirectional conversion circuit

Info

Publication number
JPS56138350A
JPS56138350A JP4226380A JP4226380A JPS56138350A JP S56138350 A JPS56138350 A JP S56138350A JP 4226380 A JP4226380 A JP 4226380A JP 4226380 A JP4226380 A JP 4226380A JP S56138350 A JPS56138350 A JP S56138350A
Authority
JP
Japan
Prior art keywords
bidirectional
flop
flip
bus
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4226380A
Other languages
Japanese (ja)
Inventor
Hidenori Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4226380A priority Critical patent/JPS56138350A/en
Publication of JPS56138350A publication Critical patent/JPS56138350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1461—Suppression of signals in the return path, i.e. bidirectional control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Communication Control (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

PURPOSE:To enable the information transmission of the both buses at ''L'' state, by preventing a plurality of device lines connected to the bidirectional bus with flip- flop and clock from being at ''L'' at the same time, in the conversion circuit of bidirectional and unidirectional buses. CONSTITUTION:The input terminal IN of the RS flip-flop 1 is connected to the bidirectional bus 2, and the output terminal (d) is connected to the unidirectional bus 3 at transmission side. The clock signal CLOCK is given to the CK input of the flip- flop 1, and the signal from the unidirectional bus 4 at reception side of delayed with the signals of the output (d) of flip-flop 1, clock signal CLOCK and signal of the unidirectional bus 3 at reception side by means of the D type flip-flop 7, AND gates 8, 3 and 3-state gate 6. Thus, when the information is transmitted from one device connected to the bidirectional bus 2, the other lines are prevented from being at ''L'' for the bidirectional bus at the same time.
JP4226380A 1980-03-31 1980-03-31 Bidirectional and undirectional conversion circuit Pending JPS56138350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4226380A JPS56138350A (en) 1980-03-31 1980-03-31 Bidirectional and undirectional conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4226380A JPS56138350A (en) 1980-03-31 1980-03-31 Bidirectional and undirectional conversion circuit

Publications (1)

Publication Number Publication Date
JPS56138350A true JPS56138350A (en) 1981-10-28

Family

ID=12631139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4226380A Pending JPS56138350A (en) 1980-03-31 1980-03-31 Bidirectional and undirectional conversion circuit

Country Status (1)

Country Link
JP (1) JPS56138350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201763A (en) * 1984-03-27 1985-10-12 Seika Sangyo Kk Data transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201763A (en) * 1984-03-27 1985-10-12 Seika Sangyo Kk Data transmission system

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