JPS56135240A - Multiplying circuit - Google Patents

Multiplying circuit

Info

Publication number
JPS56135240A
JPS56135240A JP3697180A JP3697180A JPS56135240A JP S56135240 A JPS56135240 A JP S56135240A JP 3697180 A JP3697180 A JP 3697180A JP 3697180 A JP3697180 A JP 3697180A JP S56135240 A JPS56135240 A JP S56135240A
Authority
JP
Japan
Prior art keywords
arithmetic
register
circuit
multiplicand
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3697180A
Other languages
English (en)
Other versions
JPS6236255B2 (ja
Inventor
Shinji Nishibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3697180A priority Critical patent/JPS56135240A/ja
Publication of JPS56135240A publication Critical patent/JPS56135240A/ja
Publication of JPS6236255B2 publication Critical patent/JPS6236255B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP3697180A 1980-03-25 1980-03-25 Multiplying circuit Granted JPS56135240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3697180A JPS56135240A (en) 1980-03-25 1980-03-25 Multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3697180A JPS56135240A (en) 1980-03-25 1980-03-25 Multiplying circuit

Publications (2)

Publication Number Publication Date
JPS56135240A true JPS56135240A (en) 1981-10-22
JPS6236255B2 JPS6236255B2 (ja) 1987-08-06

Family

ID=12484623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3697180A Granted JPS56135240A (en) 1980-03-25 1980-03-25 Multiplying circuit

Country Status (1)

Country Link
JP (1) JPS56135240A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538579A1 (fr) * 1982-12-23 1984-06-29 Thomson Csf Operateur elementaire, notamment pour multiplieur du type en cascade
JPS60144826A (ja) * 1984-01-05 1985-07-31 Nec Corp 演算処理装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538579A1 (fr) * 1982-12-23 1984-06-29 Thomson Csf Operateur elementaire, notamment pour multiplieur du type en cascade
JPS60144826A (ja) * 1984-01-05 1985-07-31 Nec Corp 演算処理装置

Also Published As

Publication number Publication date
JPS6236255B2 (ja) 1987-08-06

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