JPS56133833A - Shaping of thin layer - Google Patents

Shaping of thin layer

Info

Publication number
JPS56133833A
JPS56133833A JP3613080A JP3613080A JPS56133833A JP S56133833 A JPS56133833 A JP S56133833A JP 3613080 A JP3613080 A JP 3613080A JP 3613080 A JP3613080 A JP 3613080A JP S56133833 A JPS56133833 A JP S56133833A
Authority
JP
Japan
Prior art keywords
thin film
cap
layer
pattern
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3613080A
Other languages
Japanese (ja)
Inventor
Hiroshi Kaneko
Naohiro Monma
Osamu Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3613080A priority Critical patent/JPS56133833A/en
Publication of JPS56133833A publication Critical patent/JPS56133833A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Abstract

PURPOSE:To form a thin film pattern with predetermined shape without applying a resist by immersing the whole body in etchants under the condition that a cap having a predetermined-shaped external frame is applied to a thin film layer provided on a substrate. CONSTITUTION:An Si substrate 1 providing with a thin film layer 2 of Al or the like is placed on a jig stand having a mandrel 9 and a cap 6 made from tetrafluorethylene or the like and providing with a similar-figured external frame in plane shape of a formed pattern is contacted with the layer 2 and the cap 6 is pressed by the tip of a pressed jig 7 through a supporting plate 8 and the whole body is immersed in etchants by keeping the above condition and the removal of etching is applied to the unnecessary part of the layer. In this way, the pattern of a thin film layer such as an electrode or the like can be formed without applying a photoresist. Therefore, an electrode film will not be contaminated and the electrode film is also superior in reproducibility and accuracy.
JP3613080A 1980-03-24 1980-03-24 Shaping of thin layer Pending JPS56133833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3613080A JPS56133833A (en) 1980-03-24 1980-03-24 Shaping of thin layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3613080A JPS56133833A (en) 1980-03-24 1980-03-24 Shaping of thin layer

Publications (1)

Publication Number Publication Date
JPS56133833A true JPS56133833A (en) 1981-10-20

Family

ID=12461194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3613080A Pending JPS56133833A (en) 1980-03-24 1980-03-24 Shaping of thin layer

Country Status (1)

Country Link
JP (1) JPS56133833A (en)

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