JPS56128025A - Counter circuit of n notation - Google Patents
Counter circuit of n notationInfo
- Publication number
- JPS56128025A JPS56128025A JP5994180A JP5994180A JPS56128025A JP S56128025 A JPS56128025 A JP S56128025A JP 5994180 A JP5994180 A JP 5994180A JP 5994180 A JP5994180 A JP 5994180A JP S56128025 A JPS56128025 A JP S56128025A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- constituted
- feeding back
- output
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
Landscapes
- Pulse Circuits (AREA)
Abstract
PURPOSE:To make small the configuration of a counter circuit in order to lower the cost, by connecting in series in order a delay circuit which has cascaded plural units consisting of a gate circuit, a logical circuit, etc., feeding back an output of the delay circuit to the gate circuit, and feeding back an output of the first stage of the unit to the logical circuit. CONSTITUTION:The counter circuit is constituted by connecting in series in order a delay circuit which has cascaded plural units consisting of a gate circuit 8, a logical circuit 9 and an IGFET, and the first closed loop is constituted by feeding back an output of the delay circuit to the input of the gate circuit 8. Also, the second closed loop is constituted by feeding back the first stage output of the unit to the logical circuit 9. Also, one of the set signal and the reset signal is inputted to at least one unit, and the residual signal is inputted to the residual unit. In this way, in case when the number of (n) is large, a counter of (n) notation can be constituted easily as 2x=n by the shift registers SR of (x) pieces or more, and a few gates, and the number of elements can also be reduced greatly when a dynamic type SR is adopted, therefore its cost can be lowered.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5994180A JPS56128025A (en) | 1980-05-08 | 1980-05-08 | Counter circuit of n notation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5994180A JPS56128025A (en) | 1980-05-08 | 1980-05-08 | Counter circuit of n notation |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP49132092A Division JPS5158056A (en) | 1974-11-18 | 1974-11-18 | N shinkauntakairo |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56128025A true JPS56128025A (en) | 1981-10-07 |
Family
ID=13127664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5994180A Pending JPS56128025A (en) | 1980-05-08 | 1980-05-08 | Counter circuit of n notation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56128025A (en) |
-
1980
- 1980-05-08 JP JP5994180A patent/JPS56128025A/en active Pending
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