JPS56127997A - Read-only memory cell - Google Patents

Read-only memory cell

Info

Publication number
JPS56127997A
JPS56127997A JP2998580A JP2998580A JPS56127997A JP S56127997 A JPS56127997 A JP S56127997A JP 2998580 A JP2998580 A JP 2998580A JP 2998580 A JP2998580 A JP 2998580A JP S56127997 A JPS56127997 A JP S56127997A
Authority
JP
Japan
Prior art keywords
line
drain
absence
lines
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2998580A
Other languages
Japanese (ja)
Inventor
Shunichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2998580A priority Critical patent/JPS56127997A/en
Publication of JPS56127997A publication Critical patent/JPS56127997A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To realize a simple and small constitution and at the same time reduce the power consumption, by using a gate and drain for the connection terminals and then writing the information by the presence or absence of a connection between a gate and the row line. CONSTITUTION:The aluminum wiring 6 forming a row line is connected to the source 2 via the contact 8, and the gate electrode 5 is connected to the drain/row line 4 formed by a diffusion via the direct contact 9. Then the presence or absence of a contact between the row and column lnes 6 and 4 is decided by the presence or absence of the contact 8 between the line 6 and the source 2, and then the information is written. For this information, the line 6 is set at the level lower than the thershold voltage during a function of a diode via the drain and gate after precharging the lines 4 and 6 up to the prescrived level of voltage. Thus the line 4 is set at OV in case a coupling is given between the lines 4 and 6, and then the lines 6 and 4 are read out as a driving line and a reading line respectively. So is with the presence or absence of a connection between the drain and the row line as well as between the source and the column line. Thus a ROM has a simple and small constitution using just a MIS transistor plus two signal lines. As a result, no DC electric power is required for reading to reduce the power consumption.
JP2998580A 1980-03-10 1980-03-10 Read-only memory cell Pending JPS56127997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2998580A JPS56127997A (en) 1980-03-10 1980-03-10 Read-only memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2998580A JPS56127997A (en) 1980-03-10 1980-03-10 Read-only memory cell

Publications (1)

Publication Number Publication Date
JPS56127997A true JPS56127997A (en) 1981-10-07

Family

ID=12291245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2998580A Pending JPS56127997A (en) 1980-03-10 1980-03-10 Read-only memory cell

Country Status (1)

Country Link
JP (1) JPS56127997A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4834633A (en) * 1971-09-09 1973-05-21
JPS4835729A (en) * 1971-09-10 1973-05-26
JPS53121529A (en) * 1977-03-31 1978-10-24 Toshiba Corp Memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4834633A (en) * 1971-09-09 1973-05-21
JPS4835729A (en) * 1971-09-10 1973-05-26
JPS53121529A (en) * 1977-03-31 1978-10-24 Toshiba Corp Memory device

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