JPS54137246A - Memory unit - Google Patents
Memory unitInfo
- Publication number
- JPS54137246A JPS54137246A JP4412678A JP4412678A JPS54137246A JP S54137246 A JPS54137246 A JP S54137246A JP 4412678 A JP4412678 A JP 4412678A JP 4412678 A JP4412678 A JP 4412678A JP S54137246 A JPS54137246 A JP S54137246A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power
- memory
- trq1
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To reduce the number of the power terminals as well as to lower the power consumption at the memory holding time by connecting the memory cell part and the peripheral circuit part to the same power source and then applying the voltage only to the memory cell part at the time of low power voltage with no power applied to the periphery circuit part through a control circuit provided newly. CONSTITUTION:In the memory to hold the memory information with the low power voltage, memory part 11 and memory peripheral part 12 are connected to the same power source V5, and transistor TrQ1 to supply the power to part 12 is connected in series between part 12 and V5. Also, the gate of TrQ1 and V5 are connected to power supply control circuit 13 to receive the control of driver TrQ2 and Q3 connected to power source V5 via resistance R1 and R2 provided at circuit 13. Thus, TrQ3 is made conducting with TrQ2 made nonconducting when the voltage is lowered at reference potential point P4 which is detected via TrQ4-Q6 plus resistance R3, and the low voltage is applied only to part 11. At the same time, the voltage to be applied to part 12 is cut off by TrQ1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4412678A JPS54137246A (en) | 1978-04-17 | 1978-04-17 | Memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4412678A JPS54137246A (en) | 1978-04-17 | 1978-04-17 | Memory unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54137246A true JPS54137246A (en) | 1979-10-24 |
JPS5736672B2 JPS5736672B2 (en) | 1982-08-05 |
Family
ID=12682905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4412678A Granted JPS54137246A (en) | 1978-04-17 | 1978-04-17 | Memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54137246A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5674888A (en) * | 1979-11-19 | 1981-06-20 | Seiko Epson Corp | Random access memory |
US4347448A (en) * | 1980-11-07 | 1982-08-31 | Mostek Corporation | Buffer circuit for semiconductor memory |
EP0157905A2 (en) * | 1984-02-22 | 1985-10-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
EP0284276A2 (en) * | 1987-03-16 | 1988-09-28 | Donald S. Stern | Selective power gating |
US6804154B2 (en) | 2002-12-18 | 2004-10-12 | Renesas Technology Corp. | Semiconductor memory device including power generation circuit implementing stable operation |
USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
-
1978
- 1978-04-17 JP JP4412678A patent/JPS54137246A/en active Granted
Non-Patent Citations (1)
Title |
---|
IEEE JOURNAL OF SOLID-STATE CIRCUITS * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5674888A (en) * | 1979-11-19 | 1981-06-20 | Seiko Epson Corp | Random access memory |
JPS6155195B2 (en) * | 1979-11-19 | 1986-11-26 | Suwa Seikosha Kk | |
US4347448A (en) * | 1980-11-07 | 1982-08-31 | Mostek Corporation | Buffer circuit for semiconductor memory |
EP0157905A2 (en) * | 1984-02-22 | 1985-10-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
EP0284276A2 (en) * | 1987-03-16 | 1988-09-28 | Donald S. Stern | Selective power gating |
EP0284276A3 (en) * | 1987-03-16 | 1990-10-03 | Donald S. Stern | Selective power gating |
USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
US6804154B2 (en) | 2002-12-18 | 2004-10-12 | Renesas Technology Corp. | Semiconductor memory device including power generation circuit implementing stable operation |
Also Published As
Publication number | Publication date |
---|---|
JPS5736672B2 (en) | 1982-08-05 |
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