JPS56111198A - Correcting system for read only memory - Google Patents
Correcting system for read only memoryInfo
- Publication number
- JPS56111198A JPS56111198A JP1372780A JP1372780A JPS56111198A JP S56111198 A JPS56111198 A JP S56111198A JP 1372780 A JP1372780 A JP 1372780A JP 1372780 A JP1372780 A JP 1372780A JP S56111198 A JPS56111198 A JP S56111198A
- Authority
- JP
- Japan
- Prior art keywords
- address
- rom4
- corrected
- rom
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To perform substantial rewrite of ROM simply and surely, by rewriting RAM and setting the identifying switching bit, in changing the content of ROM in response to the addresses between ROM and RAM. CONSTITUTION:When an address switching latch 8 is controlled and RAM is made to a write-in mode, the content of RAM6 is corrected with the access by the address of an address register 7 corresponding to the address accessing ROM4 from a CPU5, the output 15 is 1, and the switching bit 16 is set to 1. After this correction, when readout is made via the CPU5, since the bit 16 is 0 at nonset state to the address not corrected with ROM4, the readout data of ROM4 is fed to an interface common control circuit 3 via the logical sum gate 21, and at accessing to the bits corrected, the data of ROM4 is inverted and corrected with the exclusive logical sum gate 10 to be fed to the circuit 3, allowing to rewirte the content of ROM simply and surely.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1372780A JPS56111198A (en) | 1980-02-08 | 1980-02-08 | Correcting system for read only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1372780A JPS56111198A (en) | 1980-02-08 | 1980-02-08 | Correcting system for read only memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56111198A true JPS56111198A (en) | 1981-09-02 |
Family
ID=11841269
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1372780A Pending JPS56111198A (en) | 1980-02-08 | 1980-02-08 | Correcting system for read only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56111198A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61230699A (en) * | 1985-04-05 | 1986-10-14 | Nippon Denki Kanji Syst Kk | Storage system |
-
1980
- 1980-02-08 JP JP1372780A patent/JPS56111198A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61230699A (en) * | 1985-04-05 | 1986-10-14 | Nippon Denki Kanji Syst Kk | Storage system |
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