JPS5598843A - Method of isolating semiconductor integrated circuit - Google Patents

Method of isolating semiconductor integrated circuit

Info

Publication number
JPS5598843A
JPS5598843A JP498879A JP498879A JPS5598843A JP S5598843 A JPS5598843 A JP S5598843A JP 498879 A JP498879 A JP 498879A JP 498879 A JP498879 A JP 498879A JP S5598843 A JPS5598843 A JP S5598843A
Authority
JP
Japan
Prior art keywords
isolating
layer
region
insulating
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP498879A
Other languages
Japanese (ja)
Inventor
Ginjiro Kanbara
Satoshi Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP498879A priority Critical patent/JPS5598843A/en
Publication of JPS5598843A publication Critical patent/JPS5598843A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To reduce the isolating area of isolating region for insulating and isolating a reverse conductivity type epitaxial layer grown on one conductivity type semiconductor substrate by forming a deep one conductivity region in the epiaxial layer between two shallow oxide layers formed in parallel in the isolating region when insulating and isolating the epitaxial layer.
CONSTITUTION: When an n-type layer 2 is epitaxially grown on a p-type silicon substrate 1 and isolated in an island state using an insulating region, an SiO2 film 9 and an Si3N4 film 11 are first laminated on the layer 2. Then, two openings 12 and 13 are perforated at an interval on the region to be formed with an isolating region, and heat treated, thereby forming shallow oxide layers 14 and 15 in the layer 2 exposed through the openings 12 and 13. Thereafter, the films 11 and 9 of the region surrounded by the layers 14 and 15 are removed, and a p+-type insulating region 17 is diffused in the portion 16 of the exposed layer 2, thereby isolating the layer 2 in an island state. Thus, the area required for insulating and isolating the layer 2 can be reduced, thereby obtaining an IC having high integrating degree.
COPYRIGHT: (C)1980,JPO&Japio
JP498879A 1979-01-20 1979-01-20 Method of isolating semiconductor integrated circuit Pending JPS5598843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP498879A JPS5598843A (en) 1979-01-20 1979-01-20 Method of isolating semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP498879A JPS5598843A (en) 1979-01-20 1979-01-20 Method of isolating semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5598843A true JPS5598843A (en) 1980-07-28

Family

ID=11598981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP498879A Pending JPS5598843A (en) 1979-01-20 1979-01-20 Method of isolating semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5598843A (en)

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