JPS5595343A - Container for semiconductor - Google Patents

Container for semiconductor

Info

Publication number
JPS5595343A
JPS5595343A JP325079A JP325079A JPS5595343A JP S5595343 A JPS5595343 A JP S5595343A JP 325079 A JP325079 A JP 325079A JP 325079 A JP325079 A JP 325079A JP S5595343 A JPS5595343 A JP S5595343A
Authority
JP
Japan
Prior art keywords
leads
wall
container
base
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP325079A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6146975B2 (cs
Inventor
Isamu Nagameguri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP325079A priority Critical patent/JPS5595343A/ja
Publication of JPS5595343A publication Critical patent/JPS5595343A/ja
Publication of JPS6146975B2 publication Critical patent/JPS6146975B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP325079A 1979-01-11 1979-01-11 Container for semiconductor Granted JPS5595343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP325079A JPS5595343A (en) 1979-01-11 1979-01-11 Container for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP325079A JPS5595343A (en) 1979-01-11 1979-01-11 Container for semiconductor

Publications (2)

Publication Number Publication Date
JPS5595343A true JPS5595343A (en) 1980-07-19
JPS6146975B2 JPS6146975B2 (cs) 1986-10-16

Family

ID=11552207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP325079A Granted JPS5595343A (en) 1979-01-11 1979-01-11 Container for semiconductor

Country Status (1)

Country Link
JP (1) JPS5595343A (cs)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62293624A (ja) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> Ｉｃパツケ−ジ
JPS63108756A (ja) * 1986-10-25 1988-05-13 Shinko Electric Ind Co Ltd 超高周波素子用パツケ−ジ
US4953001A (en) * 1985-09-27 1990-08-28 Raytheon Company Semiconductor device package and packaging method
JPH0524399U (ja) * 1991-09-02 1993-03-30 コクヨ株式会社 額 縁
US5574314A (en) * 1994-07-28 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including shielded inner walls

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587461A (en) * 1978-12-26 1980-07-02 Fujitsu Ltd Microwave integrated circuit package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587461A (en) * 1978-12-26 1980-07-02 Fujitsu Ltd Microwave integrated circuit package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953001A (en) * 1985-09-27 1990-08-28 Raytheon Company Semiconductor device package and packaging method
JPS62293624A (ja) * 1986-06-13 1987-12-21 Nippon Telegr & Teleph Corp <Ntt> Ｉｃパツケ−ジ
JPS63108756A (ja) * 1986-10-25 1988-05-13 Shinko Electric Ind Co Ltd 超高周波素子用パツケ−ジ
JPH0524399U (ja) * 1991-09-02 1993-03-30 コクヨ株式会社 額 縁
US5574314A (en) * 1994-07-28 1996-11-12 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device including shielded inner walls

Also Published As

Publication number Publication date
JPS6146975B2 (cs) 1986-10-16

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