JPS5589989A - Electrically erasable rom - Google Patents

Electrically erasable rom

Info

Publication number
JPS5589989A
JPS5589989A JP16487178A JP16487178A JPS5589989A JP S5589989 A JPS5589989 A JP S5589989A JP 16487178 A JP16487178 A JP 16487178A JP 16487178 A JP16487178 A JP 16487178A JP S5589989 A JPS5589989 A JP S5589989A
Authority
JP
Japan
Prior art keywords
transistor
memory
gate
fed
channel injection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16487178A
Other languages
Japanese (ja)
Inventor
Michitoku Kamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16487178A priority Critical patent/JPS5589989A/en
Publication of JPS5589989A publication Critical patent/JPS5589989A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce the cell size of memory, by performing write-in with channel injection through large current flowing to the memory transistor and performing erase through causing break down at the source side. CONSTITUTION:The isolation gate type transistor TM1 and the floating gate channel injection type memory transistor TM2 having the control gate are connected in series to constitute the memory cell Cij, the row selection output Xi is fed to the gate of the transistor TM1, the drain is connected to the column selection means Yj, control signal VcG is fed to the control gate of transistor TM2, and control circuit signal VcL is fed to the source. The write-in is made with channel injection through greater current flowing to the transistor TM2, and erase is made by causing breakdown at the source of the transistor TM2. Thus, the cell size of memory can be reduced.
JP16487178A 1978-12-27 1978-12-27 Electrically erasable rom Pending JPS5589989A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16487178A JPS5589989A (en) 1978-12-27 1978-12-27 Electrically erasable rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16487178A JPS5589989A (en) 1978-12-27 1978-12-27 Electrically erasable rom

Publications (1)

Publication Number Publication Date
JPS5589989A true JPS5589989A (en) 1980-07-08

Family

ID=15801503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16487178A Pending JPS5589989A (en) 1978-12-27 1978-12-27 Electrically erasable rom

Country Status (1)

Country Link
JP (1) JPS5589989A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113489A (en) * 1981-01-07 1982-07-14 Nec Corp Semiconductor storage device
EP0087012A2 (en) * 1982-02-19 1983-08-31 International Business Machines Corporation Electrically alterable read-only storage cell and method of operating same
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113489A (en) * 1981-01-07 1982-07-14 Nec Corp Semiconductor storage device
JPS6126157B2 (en) * 1981-01-07 1986-06-19 Nippon Electric Co
EP0087012A2 (en) * 1982-02-19 1983-08-31 International Business Machines Corporation Electrically alterable read-only storage cell and method of operating same
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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