JPS5582468A - Insulating gate type field effect transistor and its preparation - Google Patents

Insulating gate type field effect transistor and its preparation

Info

Publication number
JPS5582468A
JPS5582468A JP15709778A JP15709778A JPS5582468A JP S5582468 A JPS5582468 A JP S5582468A JP 15709778 A JP15709778 A JP 15709778A JP 15709778 A JP15709778 A JP 15709778A JP S5582468 A JPS5582468 A JP S5582468A
Authority
JP
Japan
Prior art keywords
type
region
channel
oxide film
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15709778A
Other languages
Japanese (ja)
Inventor
Yoshiki Tanigawa
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP15709778A priority Critical patent/JPS5582468A/en
Publication of JPS5582468A publication Critical patent/JPS5582468A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To accurately control the width of a channel region, and to improve yield, by separating a portion between a source and a drain of a double diffusion type IG-FET by means of a groove, and by mounting a gate electrode into the groove through an insulating layer. CONSTITUTION:A p-type channel dope region 2 is formed by selectively diffusing p-type impurities to a p-type semiconductor substrate 1 with low concentration from a window 5 of an oxide film mask 6. An n<+>-type region 7, which is shallower than the p-type region 2 and which one portion stacks to the region 2, is selectively made up by using the other oxide film mask. The n<+>-type region 7 is divided into two independent regions 3, 4 by etching the substrate in an aeolotropic shape from a window 8 of the oxide film 6' again built up, and a concave portion 9 is formed so that the channel dope region 2 be exposed. A gate electrode G is mounted to the concave portion 9 through a gate insulating film 10, and a source electrode S and a drain electrode D are installed to the n<+>-type regions 3, 4. Thus, the width of the channel can precisely be controlled.
JP15709778A 1978-12-14 1978-12-14 Insulating gate type field effect transistor and its preparation Pending JPS5582468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15709778A JPS5582468A (en) 1978-12-14 1978-12-14 Insulating gate type field effect transistor and its preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15709778A JPS5582468A (en) 1978-12-14 1978-12-14 Insulating gate type field effect transistor and its preparation

Publications (1)

Publication Number Publication Date
JPS5582468A true JPS5582468A (en) 1980-06-21

Family

ID=15642174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15709778A Pending JPS5582468A (en) 1978-12-14 1978-12-14 Insulating gate type field effect transistor and its preparation

Country Status (1)

Country Link
JP (1) JPS5582468A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531413B2 (en) 2004-06-17 2009-05-12 Samsung Electronics Co., Ltd. Method of forming transistor having channel region at sidewall of channel portion hole

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531413B2 (en) 2004-06-17 2009-05-12 Samsung Electronics Co., Ltd. Method of forming transistor having channel region at sidewall of channel portion hole
US7767531B2 (en) 2004-06-17 2010-08-03 Samsung Electronics Co., Ltd. Method of forming transistor having channel region at sidewall of channel portion hole

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