JPS5580872A - Microprogram loading system - Google Patents

Microprogram loading system

Info

Publication number
JPS5580872A
JPS5580872A JP15328578A JP15328578A JPS5580872A JP S5580872 A JPS5580872 A JP S5580872A JP 15328578 A JP15328578 A JP 15328578A JP 15328578 A JP15328578 A JP 15328578A JP S5580872 A JPS5580872 A JP S5580872A
Authority
JP
Japan
Prior art keywords
memory
region
address
contents
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15328578A
Other languages
Japanese (ja)
Inventor
Nobuyuki Watanabe
Seijiro Tajima
Haruo Hayamizu
Naoaki Yasumi
Tsutomu Sumimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP15328578A priority Critical patent/JPS5580872A/en
Publication of JPS5580872A publication Critical patent/JPS5580872A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To prevent the mistaken alteration for the region proper to the hardware of the control memory by inhibiting the writing of the contents of the main memory into the control memory in case the address to load the contents of the main memory into the control memory is outside the designation region.
CONSTITUTION: An access is given to the address which is designated by effective address register 19 in accordance with the contents of program counter 17, and then the order is read out of main memory 1. The contents of register 16 designated by part of the order read out is used as the writing address to control memory 2 and then applied to comparator 11 via operand register 13 to be then compared with the set value of lower and upper limit region registers 9 and 10 of firm region 4 which is to be rewritten in accordance with the program of memory 2 to be applied to comparator 11. And in case the writing address is outside the firm region range, the writing is inhibited for the data given to memory 2 from memory 1 by the inhibition signal delivered from comparator 11. As a result, the alteration due to the mistaken program can be prevented for region 3 proer to the hardware of memory 2.
COPYRIGHT: (C)1980,JPO&Japio
JP15328578A 1978-12-11 1978-12-11 Microprogram loading system Pending JPS5580872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15328578A JPS5580872A (en) 1978-12-11 1978-12-11 Microprogram loading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15328578A JPS5580872A (en) 1978-12-11 1978-12-11 Microprogram loading system

Publications (1)

Publication Number Publication Date
JPS5580872A true JPS5580872A (en) 1980-06-18

Family

ID=15559122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15328578A Pending JPS5580872A (en) 1978-12-11 1978-12-11 Microprogram loading system

Country Status (1)

Country Link
JP (1) JPS5580872A (en)

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