JPS5578550A - Semiconductor and manufacture thereof - Google Patents

Semiconductor and manufacture thereof

Info

Publication number
JPS5578550A
JPS5578550A JP15166978A JP15166978A JPS5578550A JP S5578550 A JPS5578550 A JP S5578550A JP 15166978 A JP15166978 A JP 15166978A JP 15166978 A JP15166978 A JP 15166978A JP S5578550 A JPS5578550 A JP S5578550A
Authority
JP
Japan
Prior art keywords
solution
temperature
semiconductor layer
type semiconductor
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15166978A
Other languages
Japanese (ja)
Inventor
Shigeo Hachiman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15166978A priority Critical patent/JPS5578550A/en
Publication of JPS5578550A publication Critical patent/JPS5578550A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To control the concentration of impurities and lattice defects by melting again the first n-type semiconductor layer which has once grown, raising the temperatures thereof and of growth solution, and simultaneously doping impurities.
CONSTITUTION: An n-type growth solution 4 is made in a growth solution reservoir 5, and the temperature thereof is raised to 1020°C. A boat body 6 is slid until the n-type LEC substrate crystal 1 of GaP and the solution 4 contact with each other. The body 6 is slid further, and the solution 4 with a given thickness is placed on the surface of the crystal 1. The first-type semiconductor layer is let grow on the surface of the crystal 1 by lowering the temperature of the solution 4 to 930W970°C. The impurities and nitrogen which serve as illumination center are doped in the solution 4 through a through hole 7. The temperature of the solution 4 is raised at a rate of 0.2W0.6°C per min. When having reached 950W980°C, the temperature is lowered for forming the second-type semiconductor layer on the surface of the first layer.
COPYRIGHT: (C)1980,JPO&Japio
JP15166978A 1978-12-08 1978-12-08 Semiconductor and manufacture thereof Pending JPS5578550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15166978A JPS5578550A (en) 1978-12-08 1978-12-08 Semiconductor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15166978A JPS5578550A (en) 1978-12-08 1978-12-08 Semiconductor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5578550A true JPS5578550A (en) 1980-06-13

Family

ID=15523640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15166978A Pending JPS5578550A (en) 1978-12-08 1978-12-08 Semiconductor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5578550A (en)

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