JPS5577293A - Status information return system of doubled information processor - Google Patents

Status information return system of doubled information processor

Info

Publication number
JPS5577293A
JPS5577293A JP15136578A JP15136578A JPS5577293A JP S5577293 A JPS5577293 A JP S5577293A JP 15136578 A JP15136578 A JP 15136578A JP 15136578 A JP15136578 A JP 15136578A JP S5577293 A JPS5577293 A JP S5577293A
Authority
JP
Japan
Prior art keywords
information
timing
signal sts
status
sts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15136578A
Other languages
Japanese (ja)
Other versions
JPS587118B2 (en
Inventor
Shigenobu Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53151365A priority Critical patent/JPS587118B2/en
Publication of JPS5577293A publication Critical patent/JPS5577293A/en
Publication of JPS587118B2 publication Critical patent/JPS587118B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To improve processing performance by eliminating mismatching between received signals of information processors operating synchronously by interposing a one-stage FF of a latch type between FF of a network controller and an information transmitter-receiver. CONSTITUTION:Status signal STS outputted by FF14 is sent back to information transmitters SRD0 and SRD1 by interposing a latch type one-stage FF15 at a halfway point. This FF15 is supplied with signal STS from FF14 as a data input and with status read command CRS as a gate signal. When command CRS arrives at FF15 as the gate signal, namely, at timing T4, status signal STS to be sent back to a central control system is sampled and latched as signal STS', which is unchangeable until next read timing T5. As a result, a processor which samples information with delay of (DELTA) behind timing T4 read information of stable signal STS'. Therefore, no mismatching occurs even in case of the occurrence of a shift in sample timing between processors.
JP53151365A 1978-12-06 1978-12-06 Status information return method in redundant information processing equipment Expired JPS587118B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53151365A JPS587118B2 (en) 1978-12-06 1978-12-06 Status information return method in redundant information processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53151365A JPS587118B2 (en) 1978-12-06 1978-12-06 Status information return method in redundant information processing equipment

Publications (2)

Publication Number Publication Date
JPS5577293A true JPS5577293A (en) 1980-06-10
JPS587118B2 JPS587118B2 (en) 1983-02-08

Family

ID=15516940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53151365A Expired JPS587118B2 (en) 1978-12-06 1978-12-06 Status information return method in redundant information processing equipment

Country Status (1)

Country Link
JP (1) JPS587118B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074859A (en) * 1983-09-30 1985-04-27 Fujitsu Ltd Inter-system synchronizing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074859A (en) * 1983-09-30 1985-04-27 Fujitsu Ltd Inter-system synchronizing system
JPH0325065B2 (en) * 1983-09-30 1991-04-04 Fujitsu Kk

Also Published As

Publication number Publication date
JPS587118B2 (en) 1983-02-08

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