JPS6074859A - Inter-system synchronizing system - Google Patents

Abstract

PURPOSE:To attain synchronization of phase between transmission digital signals of both systems by using clocks of same phase to actuate a double-structure channel device and impressing a trigger signal to the memory part of a signal transmitting circuit after giving timing to the trigger signal with a clock of own system. CONSTITUTION:The trigger signals given from bus lead-in lines 100 and 101 receive timing temporarily with clocks 540 and 541 synchronizing with each other between both systems. Therefore the synchronization is secured between orders given from order transmitting circuits 530 and 531 even in the order modes of both systems. Thus it is possible to eliminate the overlap or drop-out of signals which is produced a using device is switched to a spare device owing to a fault, etc. in a double operation mode owing to the synchronization secured between signals transmitted from channel devices of both systems.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a digital switching system having a duplex communication channel device that operates as a working system and a standby system, and particularly relates to a digital signal transmission phase system. Regarding inter-synchronization method.

(b) Prior Art and Problems FIG. 1 shows an example of the configuration of a device related to signal transmission in a conventional digital exchange.

In FIG. 1, 100, 101 are path lead-in lines, 120.
121 is a path selection circuit, 102.103 is a path confounding line,
130 and 131 are order lines, 140 and 141 are signal transmission circuits, 110 and 111 are respectively O-system and 1-system communication path devices, 150 is a system selection circuit, 151 is a channel separation circuit, 160 and 161 are subscriber circuits, and 170 , 171 is a communication path control device. The trigger signal and order shown in FIG. 2 are sent to the bus lead-in lines 100 and 101, and the trigger signal is used to activate the path selection circuits 120 and 121, and the order is used, for example, to instruct signal transmission.

In the digital exchange shown in FIG. 1, a circuit shown in FIG. 3, for example, is used as the signal transmitting circuit 140.degree. 141 to send out a digital signal.

In the circuit of FIG. 3, 300 is an order decoder, 310
320 is an address pointer memory, and 320 is a signal memory. Address pointer memory 3 from order decoder 300
10 stores a pointer for a signal memory in a memory address corresponding to a subscriber, and the signal memory 320 automatically selects one or more signals stored sequentially from that address at the time the pointer points to it. to circuit 150.

FIG. 4 shows a timing diagram regarding the operation of the address pointer memory, particularly in a critical state where a signal phase difference occurs. In FIG. 4, in soft timing, a pointer is written to an address designated by the order decoder section, and in hard timing, the pointer is sequentially read out and sent to the signal memory. From order lines 130 and 131, memory 3
The order for writing a pointer to 10 is executed almost simultaneously on both systems.
- However, it is not completely synchronized due to the activation route from each path and the operation of the decoder circuit. In particular, if the first address write order deviates at the soft timing immediately before the first hard timing as shown in Figure 4, the signal will deviate by the time equivalent to one frame of the signal circuit to be multiplexed. There are drawbacks to this.

(,) Object of the Invention In view of the drawbacks of the prior art, it is an object of the present invention to provide an inter-system phase synchronization system that synchronizes the phases of signals sent from signal circuits of both systems.

(d) Structure of the Invention According to the present invention, a subscriber circuit for digital subscribers is connected to a duplex digital communication path device, a system selection circuit, and a demultiplexing circuit, and each communication path device When the system has a signal transmitting circuit, each signal transmitting circuit that receives a trigger signal from its own path connected to the communication path control device applies the trigger signal to a storage unit that stores the digital signal to be transmitted. In a digital exchange that sends the digital signal to the subscriber circuit, each of the communication path devices is operated with a clock of the same phase, and after retiming the trigger signal with its own system clock, it is stored in the storage section of the signal transmission circuit. This is achieved by providing an inter-system synchronization method characterized in that the phase of digital signals transmitted from both systems is synchronized by applying a signal.

(,) Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a diagram showing the configuration of the system selection circuit in the inter-system synchronization system according to the present invention, and shows the state up to the time when the order sending circuit is activated upon receiving a trigger signal from each path.

In FIG. 5, the same symbols as in FIGS. 1 to 4 indicate the same components. In Fig. 5, 510.511 is a one-system/double-system identification circuit, 512, 513 are own-system order lines,
520 and 521 are OR gates, 530 and 531 are order sending circuits, 540 and 541 are D-type frizzo flops,
550 and 551 indicate clocks, respectively. The system selection circuit shown in FIG. 5 operates according to the logic shown in FIG.

For example, when the bus lead-in line 100 is at the H level, the output of the ORDER 520 is at the H level, and the order sending circuit 5
Start 30.

Conventionally, this type of system selection circuit includes a D-type flip-flop 54.
0.541 is not used. For this reason, path drop-in line 1
52
Since 0.521 was operating, when a plurality of signals are transmitted continuously, the phase difference between the signals as described above becomes a problem.

According to this configuration, the trigger signal from the path lead-in line is once retimed by the clocks 540 and 541 that are synchronized in both systems, so even in the case 3 of FIG. Orders from .531 can be synchronized.

- 10,000, in FIG. 5, the path confounding line 102. xoa is used as a control route for the own channel device from the other path when control from the own path is impossible.

Case 4 in FIG. 6 shows that it is possible to control the self-system communication path device from the 1-system bus by setting the O-system bus to the L level.

FIG. 7 shows an example of the configuration of the system selection circuit and timing circuit. As described above, in order to control the own communication path device from the other system path, it is necessary to maintain the own system path at the L level. In the circuit shown in Fig. 5, in which a timing flip-flop is inserted for synchronization between systems, if the clock 550 supplied from the local communication path device is cut off due to a failure, the path of the O system is normal. The output of the D-type flip-flop may be held at the H level even if the Figure 7 shows path lead-in line 10.
When 0 is at L level, the timing circuit is forcibly reset and toggled to keep the output at L level, thereby avoiding problems at the time of cyclic disconnection.

(f) Effects of the Invention As explained in detail above, according to the present invention, the phases of the signals transmitted from the communication path devices of both systems are synchronized, so that the current system device is not affected during redundant operation. Even if the backup system equipment is switched due to a failure or the like, there will be no duplication or loss of signals. Furthermore, when the system selection circuit performs signal verification and monitors faults in communication path equipment, there is an advantage that no verification error will be displayed even during normal operation due to the phase difference of the signals.

When a communication path fails, the clock may not be supplied to the timing circuit for intersystem synchronization, but according to the present invention, even in such a case, it is possible to access the failed communication device from the path of another system, and maintenance diagnosis and system Another advantage is that maintenance operations such as switching can proceed smoothly.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a signal transmitting device of a conventional digital exchange, Fig. 2 is a signal formation diagram of a path lead-in line in Fig. 1,
FIG. 3 is a block diagram of the signal transmitting circuit in FIG. 1, FIG. 4 is a time chart showing the operation in FIG. 3, and FIG.
The figure shows a system selection circuit in the intersystem synchronization method according to the present invention.
FIG. 6 is a truth table explaining the operation of the circuit shown in FIG.
FIG. 7 is a configuration diagram of a retiming circuit in the method according to the present invention. 100.101...Pass lead-in line, 110...O thread communication path device, 111...1 system communication path device, 102,10
3...Path confounding line, 120,121...Path selection circuit, 130.131...Order line, 140,141...
...Signal transmission circuit, 150...System selection circuit, 151.
... Channel separation circuit, 160.161 ... Subscriber circuit, 170.171 ... Communication path control device, 300 ...
- Order decoder, 310... Address pointer memory, 320... Signal memory, 510, 511... One system/both system identification circuit, 520, 521... OR gate,
530゜531...Order sending circuit, 540.541
...D type flip-flop, 550.551...clock. Patent Applicant Fujitsu Limited Nippon Telegraph and Telephone Public Corporation Hitachi Ltd. Patent Agent Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney 1) Yukio Patent Attorney Akira Yamaguchi Figure 1110 Figure 2 1C Fig. 3 17, O Fig. 4 Fig. 5 20 21 Fig. 6 Fig. 7 Procedural Amendment Officer (Method) February 22, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1, Indication of the Case 1988 Patent Application No. 180699 No. 2, Name of the invention Intersystem synchronization method 3, Relationship with the amended person's case Name of patent applicant (522) Name of Fujitsu Corporation (422) Name of Nippon Telegraph and Telephone Public Corporation (510) Hitachi, Ltd. 4, Agent Address: 8-10-5 Toranomon-chome, Minato-ku, Tokyo 105
Date of amendment order: January 31, 1980 (shipment date) 6. Subject of amendment (1) "Detailed explanation of the invention" column of Ming #+8 (Brief explanation of one drawing of 21 specification) column (3) Drawings (Captive 6, Figure 7) 7. Contents of amendment (1) The "Detailed Description of the Invention" column of the specification will be amended as follows. (a) Book of Specification A, page 6 Lines 16-17 “As shown in Figure 6”
(b) Insert the following Table 1 between page 20 of page 66 and line 1 of page 7 of the specification 〇 Below, 9 White $1 Clothes (c) Specification page 7 line 9 r$6 Figure t[tJI11
(2nd amendment) ``Figure 6'' on page 7, line 15 of the specification has been replaced with ``Table 1'' (
=Correction 0 (e) Page 7, line 18 of the specification “Figure 7” Kaoru “Figure 6”
(2) Amend page 8, line 6 of the specification, ``Figure 7'' to ``Figure 6 j (
2 Amendments to be made 0 (2) The "Brief Description of Drawings" column of the specification shall be amended as follows. (a) Page 9, line 11 of the specification to line 12 of the WJ: ``The sixth prisoner is a truth table that explains the operation of the circuit shown in Figure 5 C2;
” to be deleted. (b) “Figure 7” on page 9, line 12 of the FJA specifications was replaced with “Figure 6”.
Figure JC sleeves are corrected. (3) Delete the drawing ``Figure 6'' and move Figure 7 forward by Figure 6C as shown in the attached sheet. 8. Attached list of category 8

Claims (1)

[Scope of Claims] 1. A subscriber circuit for digital subscribers is connected to a duplicated digital channel device, a system selection circuit, and a demultiplexing circuit, and each channel device has a signal transmission circuit. When the bird receives a signal from its own path connected to the channel control device, the trigger signal is applied to a storage unit that stores a digital signal to be transmitted to each signal transmitting circuit, and the digital signal is transmitted to the digital signal. In a digital exchange that sends signals to subscriber circuits, each of the communication path devices is operated with a clock of the same phase, and the trigger signal is retimed with its own system clock and then applied to the storage section of the signal transmission circuit. υAn inter-system synchronization method characterized by synchronizing the phases of digital signals transmitted from both systems. 2. A control route for applying an IJ signal (from the path of the own system to the communication path device of the other system), and a path selection circuit that is reset by the trigger signal in each of the communication path devices, and A timing circuit for synchronizing the systems is provided between the path and the path selection circuit, and the output of the timing circuit is reset when the signal is off, so that the retiming can be performed even in the black or disconnection state. By configuring the circuit so that the signal is not kept in the ON state, even if the own path has a failure and the clock input to the retiming circuit is disconnected, the path selection is possible. 2. The intersystem synchronization system according to claim 1, wherein the circuit is not held in a set state, and the communication path device of the own system can be accessed from the path of the other system.