JPH0325065B2 - - Google Patents

Description

[Detailed description of the invention]

(a) Technical Field of the Invention The present invention relates to a digital switching system having a duplex communication path device operating as a working system and a standby system, and more particularly to an intersystem synchronization system for the transmission phase of digital signals. (b) Prior Art and Problems FIG. 1 shows an example of the configuration of a device related to signal transmission in a conventional digital exchange. In Figure 1, 100 and 101 are bus entrance lines,
120, 121 are bus selection circuits, 102, 103
is the bus confounding line, 130 and 131 are the order lines, 14
0 and 141 are signal transmission circuits, 110 and 111 are 0 and 1 system communication path devices, respectively, 150 is a system selection circuit, 151 is a channel separation circuit, 160 and 1
61 is a subscriber circuit, and 170 and 171 are communication path control devices. There is a second line on bus entrance lines 100 and 101.
The trigger signal and order shown in the figure are sent out, and the trigger signal is used to activate the bus selection circuits 120 and 121, and the order is used, for example, to instruct signal transmission. In the digital exchange shown in FIG. 1, a signal transmitting circuit 140,
As the circuit 141, for example, a circuit shown in FIG. 3 is used.
In the circuit of FIG. 3, 300 is an order decoder;
310 is an address pointer memory, and 320 is a signal memory. The address pointer memory 310 from the order decoder 300 stores a signal memory pointer at the memory address corresponding to the subscriber, and the signal memory 320 stores the single or multiple signals stored in order from that address at the point indicated by the pointer. It is automatically sent to the system selection circuit 150. FIG. 4 shows the timing related to the operation of the address pointer memory, and particularly shows a timing diagram in a critical state where a signal phase difference occurs. In FIG. 4, in soft timing, a pointer is written to an address designated by the order decoder section, and in hard timing, the pointer is sequentially read out and sent to the signal memory. From the order lines 130 and 131, the memory 31
Orders for writing a pointer to 0 are sent almost simultaneously in both systems, but they are not completely synchronized due to the activation route from each bus and the operation of the decoder circuit. In particular, if the i-th address write order deviates at the soft timing immediately before the i-th hard timing as shown in Figure 4, the signal will deviate by the time equivalent to one frame of the multiplexed signal circuit. There are drawbacks. (c) Object of the Invention In view of the drawbacks of the prior art, it is an object of the present invention to provide an intersystem phase synchronization system that synchronizes the phases of signals sent from signal circuits of both systems. (d) Structure of the Invention According to the present invention, a subscriber circuit corresponding to a digital subscriber is connected to a duplex digital channel device, a system selection circuit, and a demultiplexing circuit, and each channel device receives a signal. When having a transmitting circuit,
Applying the trigger signal to a storage section that stores digital data to be transmitted to each of the signal transmitting circuits that has received a trigger signal from a bus of its own system connected to the communication path control device, and transmitting the digital signal to the subscriber circuit. In the transmitting digital exchange, each of the communication path devices is operated with a clock of the same phase and has a control route for applying a trigger signal from the bus of its own system to the communication path device of another system, and a control route for each of the communication path devices. A bus selection circuit that is set and reset by the trigger signal is provided, and a retiming circuit for synchronizing the systems is provided between the bus and the bus selection circuit, and the output of the retiming circuit is output when the trigger signal is off. By configuring the circuit so that the output of the retiming circuit is not held in the trigger signal ON state even when the clock is disconnected, it is possible to prevent the clock input to the retiming circuit from being disconnected when the own bus is in trouble. This is achieved by providing an inter-system synchronization method characterized in that the bus selection circuit is not held in the set state even if the bus selection circuit is in a set state, and the communication path device of the own system can be accessed from the bus of another system. (e) Embodiments of the invention Examples according to the present invention will be described in detail below with reference to the drawings. FIG. 5 is a diagram showing the configuration of the system selection circuit in the inter-system synchronization system according to the present invention, and shows the state up to the time when the order sending circuit is activated upon receiving a trigger signal from each bus. In FIG. 5, the same symbols as in FIGS. 1 to 4 indicate the same components. In Figure 5, 5
10,511 is a single system/double system identification circuit, 512,5
13 is a local order line, 520, 521 are OR gates, 530, 531 are order sending circuits, 540,
541 is a D-type flip-flop, 550, 55
1 indicates a clock. The system selection circuit shown in FIG. 5 operates according to the truth table shown in Table 1 below. For example, when the bus lead-in line 100 is at the H level, the output of the OR gate 520 becomes the H level and activates the order sending circuit 530.

[Table] Conventionally, D-type flip-flops 540 and 541 have been used in this type of system selection circuit. For this reason, since the gates 520 and 521 were operating in response to the trigger signal from the bus lead-in line 100 or 101, when multiple signals are transmitted continuously, the phase difference between the signals as described above becomes a problem. .
According to this configuration, the trigger signal from the bus lead-in line is once retimed by the clocks 540 and 541 that are synchronized in both systems, so even in the case of a two-system order as shown in Case 3 of Table 1, the order sending circuit 5
Orders from 30,531 can be synchronized. On the other hand, in FIG.
03 is used as a control route from the other system bus to the own system communication path device when control from the own system bus is impossible. Case 4 in Table 1 shows that the 0 system bus can be controlled from the 1 system bus by setting the 0 system bus to L level. FIG. 6 shows an example of the configuration of the retiming circuit of the system selection circuit. As described above, in order to control the own communication path device from the other system bus, it is necessary to hold the own system bus at the L level. In the circuit shown in FIG. 5 in which a D-type flip-flop for timing is inserted for synchronization between systems, the clock 550 supplied from the own system communication path equipment is used.
If the input is cut off due to a failure, the output of the D-type flip-flop may be held at H level even if the 0-system bus is normal. In FIG. 6, when the bus lead-in line 100 is at L level, the retiming circuit is forcibly reset to maintain the output, thereby avoiding the problem when the clock is cut off. (f) Effects of the invention As explained in detail above, according to the present invention,
Since the phases of the signals transmitted from the communication path devices of both systems are synchronized, duplication or loss of signals will not occur even if switching to the standby system device occurs due to a failure of the active system device during duplex operation. Further, even when signals are verified in the system selection circuit to monitor faults in communication path devices, there is an advantage that verification errors will not be displayed even during normal operation due to the phase difference of the signals. In the event of a communication path failure, the clock may not be supplied to the timing circuit for inter-system synchronization, but according to the present invention, even in such a case, access to the faulty communication device from the bus of another system is possible, and maintenance diagnosis and system switching are possible. There is also the advantage that maintenance operations such as these can be carried out.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a signal transmission device of a conventional digital exchange, Fig. 2 is a signal formation diagram of a bus lead-in line in Fig. 1, Fig. 3 is a block diagram of a signal transmission circuit in Fig. 1, and Fig. 4 is a block diagram of a signal transmission circuit in Fig. 1. FIG. 5 is a time chart showing the operation in FIG. 3, FIG. 5 is a block diagram of a system selection circuit in the intersystem synchronization method according to the present invention, and FIG. 6 is a configuration diagram of a retiming circuit in the system according to the present invention. 100, 101...Bus lead-in line, 110...0 system communication path device, 111...1 system communication path device, 102,1
03... Bus confounding line, 120, 121... Bus selection circuit, 130, 131... Order line, 140, 141
...Signal transmission circuit, 150...System selection circuit, 151...
Channel separation circuit, 160, 161...Subscriber circuit, 170, 171...Speech path control device, 300...
Order decoder, 310...Address pointer memory, 320...Signal memory, 510,511...One system/both system identification circuit, 520,521...OR gate, 530,531...Order sending circuit, 540,
541...D type flip-flop, 550,551
…Krotsuk.

Claims (1)

[Claims] 1. When a subscriber circuit corresponding to a digital subscriber is connected to a duplex digital communication path device by a system selection circuit and a demultiplexing circuit, and each communication path device has a signal transmission circuit, it is connected to a communication path control device. In a digital exchange that applies the trigger signal to a storage unit that stores a digital signal to be transmitted to each of the signal transmission circuits that receives a trigger signal from a bus of its own system and transmits the digital signal to the subscriber circuit, a control route for operating each of the communication path devices with clocks of the same phase and applying a trigger signal from the bus of the own system to the communication path devices of the other system;
Each of the communication path devices is provided with a bus selection circuit that is set and reset by the trigger signal, and a retiming circuit for synchronizing the systems is provided between the bus and the bus selection circuit, and the retiming circuit By configuring the circuit so that the output is reset when the trigger signal is off and the output of the retiming circuit is not held in the trigger signal on state even when the clock is disconnected, the retiming circuit An inter-system synchronization system characterized in that even if a clock input to a bus is disconnected, the bus selection circuit is not held in a set state, and access to the own system's communication path device is made possible from the other system's bus.