JPS5827719B2 - System switching method for line switching equipment - Google Patents

System switching method for line switching equipment

Info

Publication number
JPS5827719B2
JPS5827719B2 JP7153479A JP7153479A JPS5827719B2 JP S5827719 B2 JPS5827719 B2 JP S5827719B2 JP 7153479 A JP7153479 A JP 7153479A JP 7153479 A JP7153479 A JP 7153479A JP S5827719 B2 JPS5827719 B2 JP S5827719B2
Authority
JP
Japan
Prior art keywords
line
switching
switching device
line switching
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7153479A
Other languages
Japanese (ja)
Other versions
JPS55163996A (en
Inventor
衛 千野
光 増島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7153479A priority Critical patent/JPS5827719B2/en
Publication of JPS55163996A publication Critical patent/JPS55163996A/en
Publication of JPS5827719B2 publication Critical patent/JPS5827719B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Description

【発明の詳細な説明】 本発明は、二重化構成の回線交換装置の切替えを行なう
回線交換装置の系切替方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system switching system for line switching equipment that performs switching of line switching equipment in a duplex configuration.

時分割交換機に於ける空間スイッチや時間スイッチを含
む回線交換装置は、二重化されているのが一般的である
Line switching equipment including space switches and time switches in a time division switch is generally duplicated.

例えば第1図に示すように、回線交換装置2a 、2b
は主制御装置1によって同時に制御されて時分割交換動
作を行ない、回線選択装置3は、回線と回線交換装置2
a 、2bとの間の多重化並びに多重分離を行なうもの
で、クロックCLKを回線交換装置2a 、2bに供給
するクロック発生部4は共用化されている。
For example, as shown in FIG. 1, line switching devices 2a and 2b
are simultaneously controlled by the main controller 1 to perform time division switching operations, and the line selection device 3 selects the line and the line switching device 2.
The clock generating section 4 that supplies the clock CLK to the circuit switching devices 2a and 2b is shared.

又回線交換装置2a 、2bのアドレスカウンタ等の同
期化を行なう為に相互に同期信号5YNCを相手装置へ
供給し、回線交換装置2a 、2bを同期動作させてい
る。
In addition, in order to synchronize the address counters, etc. of the line switching devices 2a and 2b, a synchronization signal 5YNC is mutually supplied to the other device, thereby causing the line switching devices 2a and 2b to operate synchronously.

前述の如き従来例に於いては、二重化構成の回線交換装
置2a 、2bは完全に同期化されているので、任意の
時点で切替えることが可能である。
In the conventional example as described above, the duplex circuit switching devices 2a and 2b are completely synchronized, so that they can be switched at any time.

しかし、クロック発生部4が共用化されているので、ク
ロック発生部4の障害によりシステムダウンとなる欠点
がある。
However, since the clock generating section 4 is shared, there is a drawback that a failure of the clock generating section 4 may cause the system to go down.

本発明は、前述の如き欠点を改善したもので、その目的
は、クロック発生部も二重化して信頼性を向上し、且つ
クロック発生部の二重化による回線交換装置の同期ずれ
で、切替時に各回線に誤情報が送出されるのを防止する
ことにある。
The present invention has improved the above-mentioned drawbacks.The purpose of the present invention is to improve reliability by duplicating the clock generating section, and to prevent synchronization of the line switching equipment due to the duplicating of the clock generating section. The aim is to prevent false information from being sent out.

以下実施例について詳細に説明する。Examples will be described in detail below.

第2図は本発明の実施例のブロック線図であり、第1図
と同一符号は同一部分を示し、4 a 、4 bばクロ
ック発生部である。
FIG. 2 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts, and 4 a and 4 b are clock generators.

このようにクロック発生部4a、、4bを回線交換装置
2 a + 2 b対応に設けたことにより、各回線交
換装置2a 、2bは主制御装置1によって同時に制御
されるとしても、クロック発生部4a 、4b相互の僅
かな□相差がアドレスカウンタ等により累積されて同期
がずれたものとなる。
By providing the clock generators 4a, 4b corresponding to the line switching devices 2a + 2b in this way, even if the respective line switching devices 2a, 2b are controlled simultaneously by the main controller 1, the clock generators 4a, 4b , 4b is accumulated by an address counter or the like, resulting in an out-of-synchronization.

そこで回線交換装置2a 、2bの切替えを行なう場合
は、回線選択装置3から各回線に送出する信号を一時停
止Eシ、送受信号の時間関係が正常化された時点で、信
号送出を再開するものである。
Therefore, when switching between the line switching devices 2a and 2b, the signal sent from the line selection device 3 to each line is temporarily stopped, and the signal transmission is resumed when the time relationship between the transmitted and received signals is normalized. It is.

第3図は回線選択装置の要部ブロック線図であり、Aa
、Ab、A1〜A6はアンド回路、Na。
FIG. 3 is a block diagram of the main parts of the line selection device, and Aa
, Ab, A1 to A6 are AND circuits, and Na.

Nb、N1ばナンド回路、DECはデコーダ、MPXは
マルチプレクサ、SBは送信バッファ、FFはフリップ
フロップ、ADRは回線アドレスRDは受信データ、S
Dは送信データ、WSTBは書込ストローブ信号、S
T a 、S T bは停止信号、SELは選択信号で
ある。
Nb, N1 are NAND circuits, DEC is a decoder, MPX is a multiplexer, SB is a transmission buffer, FF is a flip-flop, ADR is a line address, RD is a received data, S
D is transmission data, WSTB is write strobe signal, S
T a and S T b are stop signals, and SEL is a selection signal.

回線交換装置2aを現用系、回線交換装置2bを予備系
とすると、停止信号STaはj Q 11、選択信号S
ELは′″09+となってむり、アンド回路Aa 、A
I 、A3 、A5が開かれる。
If the line switching device 2a is the active system and the line switching device 2b is the backup system, the stop signal STa is jQ 11, and the selection signal S
EL becomes ``09+'', and the AND circuit Aa, A
I, A3 and A5 are opened.

従って回線交換装置2aからの回線アドレスADRがデ
コーダDECとマルチプレクサMPXとに加えられ、ア
ンド回路Aaを介した書込ストローブ信号WSTBがア
ンド回路A5を介してデコーダDECに加えられたとき
、回線アドレスADHにより指定された回線対応の送信
バッファSBのフリップフロップFFのクロック端子C
にデコーダ出力が加えられ、回線交換装置2aからの送
信データSDがフリップフロップFFのデータ端子りに
加えられてセットされ、その出力が送信線に送出される
Therefore, when the line address ADR from the line switching device 2a is applied to the decoder DEC and the multiplexer MPX, and the write strobe signal WSTB via the AND circuit Aa is applied to the decoder DEC via the AND circuit A5, the line address ADR The clock terminal C of the flip-flop FF of the transmission buffer SB corresponding to the line specified by
The decoder output is applied to the decoder output, the transmission data SD from the line switching device 2a is applied to the data terminal of the flip-flop FF and set, and the output is sent to the transmission line.

又受信線のデータはマルチプレクサMPXに於いて回線
アドレスADRに従って多重化され、回線交換装置2a
、2bに受信データRDとして加えられ、主制御装置
による制御に従って時分割交換が行なわれ、送信データ
SDとなる。
Also, the data on the receiving line is multiplexed in the multiplexer MPX according to the line address ADR, and the data is sent to the line switching device 2a.
, 2b as received data RD, time-division exchange is performed under the control of the main controller, and becomes transmitted data SD.

回線交換装置2aの障害又はクロック発生部4aの障害
等により予備系の回線交換装置2b側へ切替える場合、
停止信号STa 、STbを1″としてアンド回路Aa
、Abを閉じ、書込ストローブ信号WSTBの送出を停
止する。
When switching to the standby circuit switching device 2b due to a failure in the circuit switching device 2a or a failure in the clock generation unit 4a,
AND circuit Aa with stop signals STa and STb as 1''
, Ab are closed and the sending of the write strobe signal WSTB is stopped.

従って送信線へのデータ送出は停止される。Therefore, data transmission to the transmission line is stopped.

次に選択信号SELを1″とし、アンド回路AI、A3
゜A5を閉じ、アンド回路A2.A4.A6を開き、回
線交換装置2bからの回線アドレスADRをアンド回路
A2を介してデコーダDEC及びマルチプレクサMPX
に加えられ、受信データRDを主制御装置1からの制御
によって時分割交換した回線交換装置2bからの送信デ
ータSDは送信バッファSBに加えられる。
Next, the selection signal SEL is set to 1'', and the AND circuits AI and A3
゜A5 is closed, AND circuit A2. A4. A6 is opened, and the line address ADR from the line switching device 2b is sent to the decoder DEC and multiplexer MPX via the AND circuit A2.
The transmission data SD from the line switching device 2b, which has time-division exchanged the received data RD under the control of the main control device 1, is added to the transmission buffer SB.

しかし、停止信号STbが“1″の間は書込ストローブ
信号WSTBが出力されないので、送信バッファSBに
は送信データSDはセットされない。
However, since the write strobe signal WSTB is not output while the stop signal STb is "1", the transmission data SD is not set in the transmission buffer SB.

回線交換装置2bからの回線アドレスADRに従って多
重化された受信データRDと、時分割交換されて送信バ
ッファSBに加えられる送信データSDが回線アドレス
ADRによって多重分離される関係が確立された時点で
停止信号STbをu O+yとし、書込ストローブ信号
WSTBをアンド回路A6を介してデコーダDECに加
え、回線アドレスADRのデコードを行なって、送信バ
ッファSHに送信データSDのセットを行ない、送信線
にデータの送出を開始する。
Stops when a relationship is established in which the received data RD multiplexed according to the line address ADR from the line switching device 2b and the transmitted data SD which is time-division exchanged and added to the transmission buffer SB are demultiplexed according to the line address ADR. The signal STb is set to uO+y, the write strobe signal WSTB is applied to the decoder DEC via the AND circuit A6, the line address ADR is decoded, the transmission data SD is set in the transmission buffer SH, and the data is transferred to the transmission line. Start sending.

前述の如く、回線交換装置2a 、2bの切替えに於い
て、一時的に送信データの送出を中止することにより、
その間に受信と送信との回線アドレスの関係が確立され
るので、切替時に送信線に誤ったデータが送1廿される
ことがなくなり、例えば端末装置の制御データが誤った
回線に送出されて誤動作を生じるようなことが防止され
る。
As mentioned above, when switching between the line switching devices 2a and 2b, by temporarily stopping the transmission of data,
During this time, the relationship between the receiving and transmitting line addresses is established, so incorrect data will not be sent to the sending line at the time of switching, and, for example, control data for a terminal device may be sent to the wrong line, resulting in malfunction. This will prevent things like this from happening.

以上説明したように、本発明は、二重化構成の回線交換
装置2ay2bにそれぞれクロック発生部4a、4bを
設けたことにより、一方のクロック発生部に障害が発生
しても、他方のクロック発生部からクロックを供給され
る回線交換装置により時分割交換を継続することができ
、又回線交換装置2 a 、2 b間の同期信号の相互
転送を行なわないので、回路構成が簡単になる。
As explained above, in the present invention, by providing the clock generation units 4a and 4b in the line switching device 2ay2b with a duplex configuration, even if a failure occurs in one clock generation unit, the clock generation unit 2ay2b is provided with the clock generation units 4a and 4b. Time-division switching can be continued by the circuit switching device supplied with the clock, and the circuit configuration is simplified because there is no mutual transfer of synchronization signals between the circuit switching devices 2 a and 2 b.

従って回線交換装置2ay2bは完全な同期動作ではな
いので、切替時は一時的に送信データの送出を停+hL
、切替の過渡時に於ける回線指定の誤りで誤りデータが
送出されることを防止[〜、受信データと送信データと
の回線アドレスの関係が確立する時間が予め推測し得る
ので、その時間の経過後に送信データの送出を再開して
切替を完了するものである。
Therefore, since the line switching device 2ay2b does not operate completely synchronously, it temporarily stops transmitting data during switching.
, Preventing the transmission of erroneous data due to an error in line specification during the transition of switching [~, since the time for establishing the line address relationship between the received data and the transmitted data can be estimated in advance, the elapsed time Afterwards, the transmission of the transmission data is restarted to complete the switching.

このようにして端末装置等に対する誤動作を生じさせる
こ・となく回線交換装置の現用系から予備系への切替え
を行なうことができる。
In this way, switching from the active system to the standby system of the line switching device can be performed without causing malfunctions to the terminal equipment or the like.

【図面の簡単な説明】 第1図は従来の時分割交換機のブロック線図、第2図は
本発明の実施例のブロック線図、第3図は回線選択装置
の要部ブロック線図である。 1は主制御装置、2a 、2bは回線交換装置。 3は回線選択装置、4a 、4bはクロック発生部、D
ECはデコーダ、MPXはマルチプレクサ、ADRは回
線アドレス、RDは受信データ、SDは送信データ、W
STBは書込ストローブ信号、STa、STbは停止信
号、SELは選択信号である。
[Brief Description of the Drawings] Fig. 1 is a block diagram of a conventional time division switch, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of main parts of a line selection device. . 1 is a main controller, 2a and 2b are line switching devices. 3 is a line selection device, 4a and 4b are clock generators, D
EC is a decoder, MPX is a multiplexer, ADR is a line address, RD is received data, SD is sent data, W
STB is a write strobe signal, STa and STb are stop signals, and SEL is a selection signal.

Claims (1)

【特許請求の範囲】[Claims] 1 二重化構成の回線交換装置と、各回線交換装置に設
けたクロック発生部と、各回線交換装置に於ける時分割
交換動作を同時に制御する主制御装置と、前記各回線交
換装置と回線との間の多重化並びに多重分離を行なう回
線選択装置とを備え、前記回線交換装置の切替時に、送
信データの送出を一時停止し、次に現用系から予備系へ
の回線交換装置の切替えを行ない、切替えにより予備系
から現用系となった回線交換装置により受信データと送
信データとの回線アドレスの関係が確立されたとき、送
信データの送出を再開することを特徴とする回線交換装
置の系切替方式。
1. A line switching device with a duplex configuration, a clock generator provided in each line switching device, a main control device that simultaneously controls time division switching operations in each line switching device, and a circuit between each of the line switching devices and the line. and a line selection device that performs multiplexing and demultiplexing between the lines, and when switching the line switching device, temporarily stops transmitting data, and then switches the line switching device from the active system to the protection system, A system switching method for a line switching device, characterized in that when a line address relationship between received data and transmitted data is established by the line switching device that changes from a standby system to a working system due to switching, transmission of transmission data is resumed. .
JP7153479A 1979-06-07 1979-06-07 System switching method for line switching equipment Expired JPS5827719B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7153479A JPS5827719B2 (en) 1979-06-07 1979-06-07 System switching method for line switching equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7153479A JPS5827719B2 (en) 1979-06-07 1979-06-07 System switching method for line switching equipment

Publications (2)

Publication Number Publication Date
JPS55163996A JPS55163996A (en) 1980-12-20
JPS5827719B2 true JPS5827719B2 (en) 1983-06-10

Family

ID=13463490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7153479A Expired JPS5827719B2 (en) 1979-06-07 1979-06-07 System switching method for line switching equipment

Country Status (1)

Country Link
JP (1) JPS5827719B2 (en)

Also Published As

Publication number Publication date
JPS55163996A (en) 1980-12-20

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