JPS63152248A - Data exchange system - Google Patents

Abstract

PURPOSE:To attain synchronizing data transmission by providing a variable length data bit and a frequency adjustment bit so as to attain transparent connection even between systems not synchronized with each other. CONSTITUTION:A transmission data 7 is sent to a terminal equipment 1 via a transmission side terminal adaptor 6, a time division switch 5 and a reception side terminal adaptor 4. Bits comprised of a data bit, an expanded data bit, a frame synchronizing bit, a data length display bit and a frequency adjustment bit are sent as the unit of transmission. The difference of transmission speeds due to the frequency difference between an internal clock and an external clock 10 is absorbed by the increase/decrease in the data bit number unit transmission and the phase difference between the internal clock and the external clock 10 is transmitted by using a frequency adjustment bit to allow the reception side to reproduce the external clock. Thus, the transparent connection not causing any slip in the synchronizing transmission between two system not synchronized with each other is constituted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data exchange system using a time division switch, and particularly to terminals that are not synchronized with the internal clock of the switch or terminals housed in a data network and the switch. The present invention relates to a synchronous data communication method in an external clock mode in which data is transmitted using a clock (hereinafter referred to as an external clock) from a terminal or data network that is not synchronized.

[Conventional technology]

In the synchronous data communication system, data is transmitted and received using synchronized reception and transmission clocks, which are different from those in asynchronous data communication. The receiving clock is always supplied from the data transmitting side, but the transmitting clock may be in internal clock mode depending on the direction in which it is supplied.

There is an external clock mode. Here, the internal clock mode is for transmitting data according to the clock supplied from the own system, and the external clock mode is for transmitting data according to the clock from the partner system. Conventionally, time-sharing exchanges have only been able to operate in an internal clock mode in which both the receive clock and transmit clock are supplied from the own system.

A conventionally possible connection system diagram is shown in FIG. 4 and will be explained.

In the figure, 1 indicates a terminal housed in the exchange, and 9 indicates an external terminal or public data network. In FIG. 4, a case will be explained in which data is transmitted from this external terminal or public data network 9 to terminal 1. .

Transmission data T from the terminal or the public data network 9 is transmitted by the internal clock 8 from the sending terminal adapter 6 . Then, the transmission data T is sent to the terminal adapter 6.
The signal is then transmitted to the terminal adapter 4 on the receiving side via the time division switch 5. The terminal adapter 4 sends the received data 2 to the terminal 1 together with the received synchronized clock 3.

That is, in this case, the transmission synchronization clock and reception synchronization clock are supplied from the Ime system.

[Problem that the invention seeks to solve]

In the conventional connection form described above, the terminal is housed in the exchange,
There were no problems with data communication between devices, but
In the case of a system that has its own clock, such as a public data network, there is a limit to how much it can be operated using only the clock from the own system. That is, as shown in FIG. 3, which is a connection system diagram that allows multiple connections according to the present invention, it is necessary to enable data transmission using an external clock 10 from an external terminal or public data network 9 to be connected. .

However, in this case, if the exchange system and the external terminal or the public data network 9 are synchronized, this can be handled relatively easily by providing a backup memory to absorb the phase shift, but if they are not synchronized, both There has been a problem in that a slight difference in the frequency of the system clocks can cause data dropouts and slips such as double transmission.

[Means for solving problems]

The data exchange system of the present invention transmits data bits, extension data bits, frame synchronization bits, data length display bits, and frequency adjustment bits as a transmission unit in data communication using a time division switch, and uses an internal clock and The difference in transmission speed due to the frequency difference with the external clock is absorbed by increasing or decreasing the number of data bits per unit transmission, and the phase difference between the internal clock and the external clock is transmitted through the frequency adjustment signal. This allows the external clock to be regenerated on the receiving side.

[Effect]

In the present invention, it is possible to configure a transparent connection in which no slip occurs even in synchronous transmission between unsynchronized systems.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the data exchange system according to the present invention, in which data is transmitted from an external terminal or public data network 9 to a terminal 1 housed in an exchange.

In FIG. 1, the same reference numerals as in FIG. 4 indicate corresponding parts, and 10 is an external clock. In the transmission side terminal adapter 6, 11 is an elastic memory, 12 is a synchronization pattern generation circuit, 13 is a selection circuit, and 14
15 is a read clock, 16 is a gate clock, 17 is a clock phase comparator, 18 is a phase comparison counter, and 19 is a multiplex circuit. Further, 20 in the receiving side terminal adapter 4 is a demultiplexing unit;
1 is frame buffer, 22 is reception, < rough memory,
23 is a reception backup memory management circuit, 24 is a reception timing control section, and 25 is a reception timing counter.

Although the present invention is basically aimed at exchanging 56 Kbp data in a time division exchange that performs switching in units of 64 Kl)p, it is also applicable to other speeds. In order to enable external clock synchronized data transmission of 56 Kb□, two 64 Kbps time slots are combined to form one frame and one transmission unit.

FIG. 2 shows the frame structure. A frame consists of the following bits.

That is, it is composed of frame synchronization bits FO+pl, data bits Do to D8, extended data bits DIN data length display bits DBL, frequency adjustment bits SCA, and signal bits S. And TS o + T
St indicates an 8-bit time slot.

Next, the meaning and role of each bit shown in FIG. 2 will be explained.

First, in order to enable application to a time-division exchange that performs switching in units of 64Ki), frame synchronization bits are set in units of 8-bit time slots.
It is designated as F1. That is, since the order between time slots is not preserved in switching in units of 64 Kbpa, it is possible to transmit a frame composed of two time slots by synchronizing in units of time slots of 64 Kl)p.

Next, data bit D is used for data transmission.

~D6 and extended data pin) Dx are provided.

When transmitting data of 56 Kbp, it is normally transmitted using 7 data bits D and 4D. However, in transmission between two systems that are not frequency synchronized, there will be a frequency difference even if the speed is adjusted to 56Kb□, so this frequency difference will cause data loss and double transmission. A so-called slip occurs.

In the present invention, in order to prevent the occurrence of this slip, the number of data bits carried per unit transmission is made variable.

In other words, when the external clock is faster than the internal clock, 8-bit transmission is performed using the extended data bit D at a cycle corresponding to the frequency difference, and when the external clock is slower than the internal clock, Data bit Do#D
, the frequency difference is absorbed by transmitting 6 bits of DQ""D5. Since the number of data bits per frame is variable in this way, a data bit length indicator (DBL) is provided to indicate the data bit length. Further, in the present invention, a frequency adjustment signal (SCA) is provided.

The data transmitted through the time division switch must be transmitted to the terminal at the same frequency as the external clock on the receiving side. If such measures are not taken, a slip will occur on the receiving side due to the frequency difference between the internal clock and the external clock.

For this purpose, on the transmitting side, the phase difference between the internal clock and the external clock is detected and the phase difference information is transmitted to the frequency adjustment bit S.
The frequency adjustment signal (CA) is added to the data bits and sent, and on the receiving side, the external clock is regenerated from the SCA information.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

As mentioned above, FIG. 1 shows the case where data is transmitted from an external terminal or public data network 9 to a terminal 1 housed in an exchange.

First, transmission data 7 from an external terminal or public data network 9 is transmitted to the terminal 1 via the transmitting terminal adapter 6, the time division switch 5, and the receiving terminal adapter 4. The external terminal or public data network 9 operates with an external clock, and the transmission data T is sent to the transmitting terminal adapter 6 in accordance with the external clock 10 from the external terminal or public data network 9. Also,
Transmission data 7 is stored in elastic memory 11 according to external clock 1G. Here, the data transmission unit is composed of bits shown in FIG. 2, and this frame is formed by the selection circuit 13. That is, frame synchronization bit FO+F1, data bit Do-D6 and extended data bit D! and data length display beep) D
BL and frequency adjustment bit 8CA are inserted into predetermined bit positions to form a frame.

An elastic memory management circuit 14 is provided for the elastic memory 11.

Further, this second stick memory 11 is provided with a jitter absorbing function by storing data up to the center of the memory in advance at the start of transmission and then starting transmission to the receiving side. Furthermore, the second stick memory management circuit 14 monitors the frequency difference between the write clock to the elastic memory 11, that is, the read clock 15 created by the external clock 10 and the internal clock, and depending on the result, Controls the read clock 15.

That is, normally the read clock gate 16 is opened for 7 bits of data bit Do#D, but if the write clock is faster than the read clock 15, the amount of data in the elastic memory 11 gradually increases. Therefore, when a predetermined level is reached, the gate is opened at the timing of the extended data pin (Ds section) and the data is read out. Conversely, if one write clock is slower than the read clock, the gate is closed at the timing of the data pin Ds to stop reading. In this way, the amount of read data is adjusted depending on the amount of data in the elastic memory 11, thereby preventing the occurrence of slips due to frequency differences.

For clock adjustment, a clock phase comparator 1T and a phase comparison counter 18 are provided. , a frequency of fi56 Kbp is generated, and the phase of this is compared with the external clock 10 in a clock phase comparator 1T.

Then, phase correction is performed by adding or subtracting the clock input to the phase comparison counter 18 based on the detection of phase lag or lead, and the corrected clock is further phase-compared with the external clock 10 to match the external clock 10. Regenerate a frequency-synchronized clock. Further, the phase difference information is sent to the receiving side as a frequency adjustment signal (SCA).

The frame formed by the process described above is further multiplexed with other data and control bits in the multiplexing circuit 19, and sent to the receiving terminal adapter 4 via the time division switch 5.

Next, the operation of the receiving side terminal adapter 4 will be explained.

First, the demultiplexer 20 separates control bits and the data frame formed by two time slots F, and these two time slots are synchronized for each time slot, and one frame is divided into 7 frames.
is stored in The data length display bit DBL in the frame is received by the reception buffer management circuit 23, and a write clock for the reception buffer memory 22 is generated according to the data length display bit DBL to write the received data.

Next, a reception timing control section 24 is used for clock control.
and a reception timing counter 25 are provided. Similarly to the phase comparison counter 18 of the transmitter, a clock of NM times 56 is input to the receive timing controller 25 via the receive timing controller 24. and,
The frequency adjustment signal (8CA) in the frame is received by the reception timing control unit 24, and the frequency adjustment signal (8CA) in the frame is
The external clock is regenerated by adjusting the number of clocks supplied to the reception timing counter 25 according to the contents of A. This regenerated external clock is used in the receive buffer memory 2.
At the same time, it is supplied as the reception synchronization clock 3 to the terminal 1.

As is clear from the foregoing, the present invention provides data bits D and ND in data communication using a time division switch.
, and extension data bit DN and frame synchronization bit F
The data consisting of O+F1, data length display bit DBL, and frequency adjustment bit SCA is transmitted as a transmission unit, and the difference in transmission speed due to the frequency difference between the internal clock and external clock is used to increase or decrease the number of data bits per unit transmission. If the phase difference between the internal clock and the external clock is transmitted by the frequency adjustment bit, the external clock can be regenerated on the receiving side.

FIG. 3 shows a connection diagram made possible by the invention.

In FIG. 3, the same parts as in FIG. 4 are given the same reference numerals, and their explanation will be omitted. 10 is an external clock.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide variable length data bits and frequency adjustment bits.
The practical effect is extremely large because it enables transparent connection and synchronous data transmission even between systems that are not synchronized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the data exchange system according to the present invention, Fig. 2 is a frame block diagram, Fig. 3 is a connection system diagram that has been made possible by the present invention, and Fig. 4 is a diagram showing a connection system that has been made possible by the present invention. FIG. 1...terminal, 4...receiving terminal adapter, 5...time division switch, 6Φ...sending terminal adapter, 9...external terminal or public data network, 11... ...Elastic memory, 12...Synchronization pattern generation circuit, 13...Selection circuit, 14...
- Elastic memory management circuit, 17... Clock phase comparator, 18... Phase comparison counter, 19...
...Multiple circuit, 20... Demultiplexer, 21...
Frame buffer, 22・φ...Receive buffer memory,
23...Reception buffer memory management circuit, 24.Φ.
- Reception timing control section, 25...reception timing counter.

Claims (1)

[Claims] In data communication using a time division switch, data bits, extended data bits, frame synchronization bits, data length display bits, and frequency adjustment bits are transmitted as a transmission unit, and transmission is based on the frequency difference between an internal clock and an external clock. The difference in speed is absorbed by increasing or decreasing the number of data bits per unit transmission, and the phase difference between the internal clock and the external clock is transmitted by the frequency adjustment bit, so that the external clock can be regenerated on the receiving side. A data exchange method characterized by the following.