JPS60120695A - Pcm frame tuning unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Accordingly, special K PCM frame synchronization unit. Related to /1.

2. Transmitted in 0 'l g Mbit/s PCM group7. ) When exchanging broadband information streams, one of the technical problems that must be addressed is maintaining the order of the individual channels of the frame as the signal passes through the time exchange stages. In particular, the channel sequence consisting of frames at the input of the exchange stage must be maintained equally at the outgoing frames. What we currently have is a bit/s bit/s bit/s for each channel as far as PCM channel exchange is concerned.
” It is Shitetake.

On the other hand, it is also useful to obtain an ordering of the individual channels in order to ensure the correct exchange of signals occupying more than /channel, for example signals coming from a video signal coding device.

In the above case, it is necessary to maintain the correct temporal order of all the individual channels forming the outgoing information stream in order to correctly reproduce the received television picture.

Currently, logic circuits are known that are capable of recognizing individual frame numbers and, within a frame, individual channel numbers. These circuits are necessary elements of the frame synchronizer BIfC because they provide initial data to maintain information flow ordering.

However, these circuits cannot intervene to perform the required synchronization.

The synchronization unit described below ensures 1> lI-
It allows the implementation of switching nodes for broadband digital streams with transmission rates of Kbit/s.

The present invention provides timing signals and synchronization signals.

Provides a PCM71/- system synchronization unit capable of synchronizing the incoming PCM frames with the PCM frames to be applied to the output supplying the IIc, ensuring the ordering of the channels belonging to the broadband information flow, said unit being one PCM
In the function of frame-related timing and synchronization signals: (1) a signal indicating whether the received channel is odd or even and controlling said first and second registers and its complement signal; (1) a large channel; , a signal indicating the channel number and frame type, a signal indicating the completion of reception of a single-channel octet, a signal indicating the beginning of a PCM frame, and a signal indicating the octet or number of single-channel octets. When the first frequency divider transmits a signal and one PCM frame is synchronized, the timing and synchronization signal functions are as follows: ,, a signal indicating whether the channel is even or odd, and its complement a+=; 1) a signal indicating the channel number to be given to the output; 1) three signals having a frequency twice the channel frequency and out of phase with each other. - a signal that adds the beginning of a PCM frame to be given to Rikisho; - a first signal having a frequency equal to half the channel frequency; - a first signal having a frequency equal to half the channel frequency; a first frequency divider for transmitting a second signal that is out of phase by a time slot compared to the second frequency divider, and one that indicates whether the received channel is odd or even; a first multiplexer capable of extracting the channel contents provided by said first or λ-th register upon reception of a enable signal; (1) a signal representative of the number of the incoming channel to be applied to the output upon command of the exchange signal; The Ωth multiplexer to be extracted and the random access memory divided into −λ partially redundant parts,
Its data input is connected to the output of said first multiplexer, its address input is connected to the output of said second multiplexer, while an input enabling writing and said - seven of the λ parts between writing. 7 of the two parts between the input and readout to allow the input and output data to be exchanged.
- a random access memory, in which inputs for exchanging one and the other are connected in a logic circuit; a synchronization register consisting of a third and a seventh register controlled by said signal indicating whether an even number is an odd number and enabled to store said first and first signals having a frequency equal to half the channel frequency; is a unit,
- said logic circuit controls said multiplexer and said random access memory in function of the signal received from said frequency divider and of the timing signal of the frame;

The above-mentioned and other features of the invention will become clearer from the following description of a preferred embodiment, given by way of illustration and not as a limitation, and from the accompanying drawings, in which: FIG.

In the following description, reference will be made to the particular case in which the PCM frame synchronization units US/, US2, US3 are so integrated into the multiple videoconference switching unit shown in the block diagram of FIG.

As is known, multiplex video conferencing systems provide for the transmission of images, audio and other signals that enable communication between people separated by λ or more different locations.

A videoconferencing system basically consists of a room with some equipment in which lectures are held and equipment used to collect and reproduce information, and a switching unit that transmits information to other connected rooms. The video information sent out from the room or other switching unit is PGM encoded at a rate of λ,0 g Mbit/s, while the audio information and the signals present are encoded at a correspondingly lower rate.

In Figure 1, US / , US 2 , US
3 shows three synchronization units provided by the present invention, which all receive a 2.0'lg Mbit/s PCM stream from a video conference room through connections/, 2 and 3. By means of bi-directional connections D, S and B, the outgoing signal stream is directed to an interlock switching stage CT, whose synchronization and timing signals are transferred to a synchronization unit US/US.
,2,tJs 3K are sent.

Next, this CT is connected to output interfaces IU/, IU, 2. by connections 71g and 9. and be connected to TO3.

The information flow that has been properly exchanged is then connected to connection 10. //,as well as/
, 2 to the video conference room.

The control unit 1-CC follows automatic criteria based on the audio level! ! Control the exchange of various treasures according to the request criteria from the people there.

(Voice Exchange Unit) The CV receives the +L audio channel transmitted from the room through connection /3, and detects the speaker channel where the audio level is noticeably distorted. This information, which controls the unit CC and is supplied through the connection /l (7), allows the implementation of exchange operations given by automatic criteria.

The exchange unit is completed by a diagnostic unit CD, which carries out appropriate checks on operation and detects possible anomalies during data exchange, both within each block and between individual blocks.

Accessed by the diagnostic unit keyboard KB, detailed test results are displayed on the monitor MOK.

The block diagram of FIG. 2 shows an individual synchronization unit, e.g.
/ indicates.

The reference numbers / and da again indicate input and output connections. In particular, connection 1/a carries a broadband incoming data stream 1~, connection/b
indicates the input data timing, and connection /C indicates the A type PCM.
It carries frame synchronization, which consists of a signal that is present for the entire duration of the frame.

Connection lla carries the output stream to be sent to the exchange stage and connects 1/1. b and 'lc carry all outgoing data timing and synchronization signals, the last two signals being provided by the exchange stage.

accessing the timing signal present on wire /b and the synchronization signal present on wire /C frequency divider 1) A;
The divider determines whether the channel number is odd or even at each point.
Give it to the output of B, and select the channel to which the divider belongs to 1 and the frame (F~], A 4 υl 13). Determine the channel sequence of the frames. Complete reception of data belonging to channel /l/ appears partially on wire /g.
tl The starting length of the frame is shown on wire 3o, and the availability of received data is shown on wire 3/(C signal).

Similarly, it does not indicate whether the channel number to be given to the frequency divider DBil-i output is odd or even.
and 20 and the commands of blocks TA and 1 13 are given to all wires 472 and l/13 - still wire lIh
and gives to connection 2/ exactly the number of the channel from which the said information is obtained from the signal sent from the exchange station throughout.

Finally, connect the timing signals necessary for the operation of the logic circuit LC. It is sent through the floodwaters and wires.

Reference symbols RA and RB designate a registers, which alternately change the contents of the incoming channel on wire /a on command of the signals present respectively on the already mentioned wires /a and /o. It's something you can remember.

MA designates a multiplexer which extracts the data supplied by register RA or RB upon command of the signals present on wires /S and /B. MA is enabled to extract data by a signal supplied by logic circuit LC through wire 2k.

MB indicates a multiplexer, and the multiplexer θ'',
Upon command of the exchange signal sent from the logic circuit LC through the wire B, the Mti number of the incoming channel or outgoing channel given by the frequency divider DA or DB is fully extracted.

The MAi wire 23 provides input data for the random access memory RAM, and the MB provides the wire 2 with a channel number to be used as a write and read address for the memory IJ RAM that stores one PCM frame.

This memory is divided into two parts, each consisting of 3.2 octets and assigned to data storage belonging to frame A1 or frame B. Read and write operations 1) [= is wire)'7. ．． 2g.

3.2 and 33 are executed in response to instructions from the logic circuit LC.

The data sent on connection 2q is connected to wire /9. from frequency divider DB. ．． 20. The data from TA or TB is transferred to one register TA and TB which is controlled alternately through the group λ,'13(i,-).The data from TA or TB is finally sent to the exchange stage Jl, Ru.

The logic circuit LC is shown in more detail in the block diagram in Figure 3 (/'C
shown.

The LC consists of λ different circuits, the second part of which is t! of the input channel octets. The bottom circuitry is designed to identify the time phase in which a write operation or a write operation of an octet of the outgoing channel is to be performed, and the circuitry at the bottom provides data to the portion of the memory in which the write or read operation is to be performed.

The method for writing to the octetram memory of the input channel is described below. If an octet is present in register RA or RB, frequency divider DA sends a signal on wire /g. This signal indicating the end of reception of an octet is stored in the register FR, and the circuit LC is thus informed that the incoming octet is almost completely written into the register RA or R]3.

This octet may then be stored in the memory RAM with the channel address received from the frequency divider DA via connection 211 and multiplexer MB, controlled by the input signals /b and /C. These signals, which are in phase with the input PCM frame, allow the frequency divider DA to detect within the entire frame the time position of the octets to be stored. This location is expressed as a lambda-adic number, which is used as the address of the memory RAM where the ocd, l' is to be stored.

At this point, said octet is written to the memory RA when it is enabled to be written by the signal on wire 32 which is received in its entirety from the frequency divider DA on wire 3/
It becomes possible to transfer to M.

The memory portion in which the above summation is carried out is determined by the register FL, which stores the logic state present on wire /C through the register 171 of wire 30.

Next, note the logical level! A signal identifying either part of the J RAM is applied to the wire, 2gVC connected output. Reading is always performed in seven parts of the memory other than the one where the congestion is progressing.

The output channel octets to be stored in register TA or TB are read out via connection 2/ to frequency divider 1).
By B, the connection is short. determined by the timing signals present at 2. For this connection, add 3 wires, 2, 2a
, 2.2b, and 2.2c, these wires are pulsed at twice the channel frequency and in proper phase relationship.

The information prestored in FR is transferred through wire SO and wire P during the time phase when the 12, 2, 2a signal is at a high logic value for register Fc. The signal sent out from the FC of the wire user B determines the position of the multiplexer MB which extracts the channel number provided by the DB. The ratio signal on wire 25 causes FC to inhibit multiplexer MA f, and the signal sent through gate P3 on twisted wire 27 enables data output from the memory.

1) 3 is controlled by the signal of wire 2Ωb.

By means of the signal on wire 22c, the Ω registers FR and FC are then reset (1) through (1), (2) controlled by the signal sent from the switching register (FC).
,! t1 Next read and fill cycle can be started. The cross/ζ signal sent from the FS detects the seven portions of the memory where the read operation is to be performed. For this, register FS (/:1 wire 3
Controlled by the signal present on 1I, the signal 3 carries an indication of the beginning of the outgoing frame, which is supplied by the signal present on the exchange stage and wire 2g, already described.

For further clarity, FIG. 7 shows the waveforms of the signals present at key points in the block diagrams of FIGS. 2 and 3. Each waveform is designated by an L, with the same number as that of the wire in which it appears. In particular, /c Id corresponds to the logic level /gan 1/-)・A, and the input frame l whose logic 1/bell 0 corresponds to frame H
It shows the timing relationship between /- and -/B.
The use of the register RA (FIG. 2) of the odd channel to determine the data storage by the logic l/bel/ indicates the possibility of -/,!r (cl, the register RB of the even channel)
indicates the ability to use =7glrJ Chi\, completely receives data from Nell (F?
L/here and -77 indicates the number of channels encoded/(person channel), -l10 indicates that the even channel data is encoded by the multiplexer M
-Il/ is present at the input of A, and the non-dashed portions indicate all the time phases corresponding to the non-valid periods of data.
Indicates all the time phases present at the inputs of A, -37 indicates the signal provided by the frequency divider DA for a write command in the memory, -2g indicates the signal provided by the frequency divider DA for a write command in the memory, and -2g indicates the signal supplied to the register FL of the circuit LC (Fig. 3). In function of the signal states on wire /C and 30 being stored: 1. Denotes the signal on the command wire that determines the use of any part of memory in the process, -30 designates the time phase of the signal that detects the beginning of the incoming frame, = IIC(/i, It is assumed here that the phase advance customer is given with respect to the input timing /C.
-79 is the frame timing of register TA (Fig. 2) of odd channel.
-, 20tri, indicates the availability of the register TB of even channels, -Sθ is in the function of fully receiving channel data (signal 7g) and memory IJ RAM by signal 32.
In the function of data recording that occurred in (FIG. 2), the time phase of the read request determined by the register FR of the circuit LC (FIG. 3) is determined by T7, 1, 2-! atd1, indicates the beginning of the time phase allocated for reading the memory RAM (FIG. 2), where the transition is transferred to the register F through the key 1 P (FIG. 3).
-23 is the phase of the signal that enables, switches or inhibits Mardizo1/Kuza MA (Fig. 2) corresponding to the logic level /l/koU, 0, respectively. , where the output signal of the wire O is its complement Tsukuda (,2,, S-== ,2,!;
), and the theory J! )2+/bell/or 0 respectively, the number of the outgoing channel received from the frequency divider 1) +3 or the number of the incoming channel received from the frequency divider DA sound wire! -22b is used to position the multiplexer MB as shown in Figure 3, and wire 27 with the possibility of being used for readout. (Fig. 2) shows the time phase of the signal that supplies the RAM. -, 2/ indicates the outgoing channel number, -, , 29 indicates that the data supplied to the wire 29 by the memory RAM (FIG. 2) is in the register TA, TB is turned on, and the data result shows the valid time phase in the part without a dash. -'%, 2 indicates the control signal of the register TA which stores the data supplied to the connection 29 by the memory RAM;
, where said signal is shown by 3 and has a frequency which is half the channel frequency, as in a), and -33 is the signal on wire 2g (FIG. 3) sent out from resistor FL. 7. Shows the signal that determines the use of any part of the memory during a write in function of the signal state, where a transition is present on wire 3 at the output of the frequency divider DA. ) is carried out in response to the return to zero of the signal indicating the beginning of the frame, and -all indicates the time phase of the signal identifying the beginning of the outgoing frame.

It is clear that the description given above is given by way of non-limiting example only. Changes and modifications to the embodiments described above are possible without departing from the scope of the invention.

[Brief explanation of drawings]

- Figure 1 is a block diagram of the video conference switching unit S: /J<, - Figure 2 is the block diagram of the video conference exchange unit S: /J<; Unit Zo 1” Tsuku 1
- Figure 3 is a detailed block diagram of the block labeled LC in Figures 2 and 2, - Figure 9 is a time diagram of the signals present at the main points of the diagrams in Figures 2 and 3. Give -. US/, US 2, US 3...PCM frame synchronization unit, /~3<7,4 steps, G3,50...Wire connection, CT/time exchange stage, IU/,
IU, 2, IU3...output interface, C
C...control unit, C■...audio exchange unit),,
CD...Diagnostic unit, KB...Keyboard, MO...
・Monitor, DA, DB・・Frequency divider, TA,
TB...Block, LC...Logic circuit, RA, R
B. 1”R, FL, FC, FS, TA, TB・
・・Register, ■Product, MB/Multiflexor, RAM
...Random access memory, 1)/~P4...ket. Agent's name: Kawahara 1) - Ho

Claims (5)

[Claims] (1) Timing signal and synchronization signal ('l b + '
I) CM frames and incoming PCM frames should be fed to an output that supplies lc) to ensure total synchronization between the CM frames and the incoming PCM frames, ensuring ordering of the channels belonging to the broadband information flow. Related individual days) Write down the contents of the 4 channels (/a) alternately one by one 1',! 'L
#! The first and Ω registers (RA, RI3
); - in function of the timing and synchronization signals (/b, /c) for the PCM frame; - fully indicates whether the received channel is bath number or even;
and the irises that control the second register and their complements (
/Otsu, /Left) and; - Displays the channel number and frame ai Ii k 1
- Signal (/7);
g) - a signal (30) indicating the beginning of a PCM frame; - a signal indicating that an octet of the channel is available (30);
3/) and; the first frequency divider (DA) and the knee person 1
``In the function of the timing and synchronization signal (+b, 4'c) at which the CM frame should be synchronized, - a signal indicating whether the channel to be given to the output is an even number or an odd number and its complement signal </q, 2θ); - a signal representing the channel number to be given to the output (
2/); - three pulse signals whose frequency is twice the channel frequency and mutually out of phase (-2-2a + -22b., 2.2e); - applied to the output and to be seen; a signal (311) indicating the beginning of a PCM frame; - a first signal C41,2> having a frequency that is half the channel frequency; - a signal (311) that has a frequency that is half the channel frequency;
A first frequency divider (1)B) which sends out a second signal (/l3) whose phase is shifted by 7 time slots compared to the signal (G, 2)K; , l
Hina-1, the signal indicating whether the channel is even or odd (/B,
/S) command, one eye can be used signal (,25)
upon reception of said seventh (RA) or said seventh (RA);
4) the first multiplexer (MA); - represents the number of the incoming channel to be provided according to the command of the exchange signal; the seed signal (/7 or; 2/); - a data input (23) is connected to the IJi power of said first multiplexer; 1.
A random 7-access memory subdivided into 1.2↑X+S, the address input (2Il-) is connected to the output of the second multiplexer, while the input (, ?, An input that switches seven of the two parts during reading (C, 2g), an input that enables the output data (,27), and an input that switches one of the two parts (33) during reading. a random access memory (RAM) connected to a logic circuit (LC);
In the third and third registers (TA, TB) which store the contents of the M channels alternately and sequentially, the signal (/9. .20), and the third and ninth registers (TA, - the logic circuit (LC) determines the function of the signal received from the frequency pollution detector (DA; DB) and the human frame (/C
) in the function of the timing signals of the multiplexers (MA, MB) and the forward access memory (
A PCM frame synchronization unit characterized in that it controls a PCM frame synchronization unit (RAM). (2) The logic circuit (LC) receives the signal (LC) indicating that the knee channel has been completely received.
7g) and the fifth renostar (FR) which stores the first signal (,2,2a) of the J pulse signal (,2,2a). Output & (m Transfer 1st key-1・(P/1.)
and; - 1 to supply the enable signal (2k) and the switching signal (2k);
Remember the signal from No. 41/JIS (FC);
), and at 10 o'clock, transfers the use signal (, 2) to the output, and outputs the output signal (, 27).
) of the random access memory (RAM).
(P3) and the signal from the sixth register and the third signal of the millimeter bow.
When the bows (, 2, 2c) are at high level at the same time, the S and 4th registers are all set - J-7,, 3rd K-)
(:P, 2) and ; -i are used to supply the signal (,J', 2) which enables the input b', by the signal indicating the '1f' requirement of the incoming channel octet). q-th port (p/l) which, when enabled, transfers the signal stored by the fifth renostar to the output; PCM frame synchronization unit. (3) The above PCM frame synchronization unit is -=9
Random access memo during 11 minutes! λ of j (RAM)
When the signal (30) of the incoming PCM frame starts supplying the seven switching signals (2g) of the two parts, the seventh renosk (1”L) stores the synchronization signal (/C).
and; - said signal (3q) indicating the beginning of the PCM frame to be provided at the output, in order to provide said signal (33) for switching seven of the a portions of random access memory (RAM) during reading; ), when receiving a call, add (25)
The fifth reno star (F
S);
PCM frame synchronization unit as described in Section. (4) Said broadband information stream (1) consisting of the contents (/a) of the individual channels of the incoming ECM frame of timing (/b) and synchronization (/C) signals is an encoded video signal; A PCM frame synchronization unit according to any one of claims 1 to 3 or claim 7, characterized in that: (5) Random access memory (+tAM) IrJ
, 1.I) CM according to claim 3, characterized in that all information contents of two PCM frames are stored.
Frame synchronization unit.