JPH0965465A - Network synchronization device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system clock synchronously with a network always stably so long as a channel in the normal operation is in existence by making the number of signal lines for network synchronizing clock signal to be supplied to the network synchronization constant regardless of the number of digital lines connecting to a public network. SOLUTION: A time switch 19 makes loopback connection to only a selected time slot of a network synchronization circuit to a same data bus at all times. Each of line interface sections 8-11 in an exchange sends a slot number inserted in the exchange to a selected time slot. The sent slot numbers are 'wired-ORed' on the selected time slot and looped back by a time switch 19 and a slot number comparison section 20 compares it with each transmission slot number for each bit. When the result of comparison indicates dissidence, the line interface sections 8-11 stop the transmission of the network synchronization clock to the network synchronization circuit 20 and when the result of comparison indicates coincidence, the sections 8-11 supply the network synchronization clock to the network synchronization circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronizer used for digital communication equipment such as digital terminals, terminal adapters, exchanges, multimedia multiplexers, etc., which needs to reproduce a network synchronization clock.

[0002]

2. Description of the Related Art FIG. 4 schematically shows an example of connection between a switchboard and a public network via a plurality of digital lines. In FIG. 4, the exchange 1 is connected to the public network 2 through the ISDN basic interface lines 3, 4, 5 and the ISDN primary rate interface line 6, and controls transmission / reception between the extension terminal 7 and the public network 2. Is going. Reference numerals 8, 9, 10, and 11 are line interface units of the respective lines 3, 4, 5, and 6 provided in the exchange 1.

Since the exchange 1 normally communicates with the public network 2, it must operate at a system clock synchronized with the network clock.

FIG. 5 is a block diagram of a conventional line interface section. In FIG. 5, reference numeral 27 denotes a frame assembling / disassembling unit, which is connected to the digital lines 3, 4, 5, or 6 to assemble and disassemble the frame according to the type of the digital lines 3-6. A unit controller 28 controls the entire line interface and communicates with the central controller inside the exchange 1. Reference numeral 29 denotes an internal data bus interface section, which is used for digital lines 3 to
Information such as voice data on 6 is connected to the internal data bus of the exchange 1 by this block. Reference numeral 31 is a network synchronization clock reproducing unit, which reproduces a clock synchronized with the network from the line data received by the frame assembling / disassembling unit 27. This recovered clock serves as a reference input clock for the intra-switch network synchronization circuit. Reference numeral 30 denotes a network synchronization clock on / off control unit, which is on when the dial lines 3 to 6 are normal. However, a failure such as line disconnection or loss of synchronization occurs at the digit lines 3 to 6, and a normal network synchronization clock is generated. When it becomes impossible to reproduce, it becomes off. Also, this network synchronization clock on / o
The unit controller 28 controls the ff controller 30.

FIG. 6 shows an example of time slot allocation in the conventional internal data bus according to the connection example of FIG.
Internal data bus is bit timing clock 2MH
z, repetition frequency 8 KHz, 32 64 Kb
Channels equivalent to ps are multiplexed. Further, in this example, three ISDN basic interface B channels are allocated to TS0 to TS5, and TS6 to TS5.
One ISDN primary rate interface B channel is assigned to the TS 28. TS29 ~ TS3
1 is an empty channel.

FIG. 7 shows an example of output control of a conventional network synchronization clock. In FIG. 7, 33 is a time switch,
Exchange connection of each time slot on the internal data bus 35 is performed. Reference numeral 34 is a network synchronization circuit (PLL), which selects one from a plurality of network synchronization clocks reproduced by the respective line interface units 8, 9, 10, 11 in the exchange 1 to make a system clock of the exchange 1 synchronized with the network. To create.

As shown in FIG. 7, even in the conventional example, each line interface section 8, 9, 10, 11 in the exchange 1 is shown.
Has a function of controlling the network synchronization clock on / off depending on the line state, so that each digital line 3, 4, 5,
As long as 6 does not go down due to a failure or the like, a normal network synchronization clock can always be supplied, and thus a system clock synchronized with the network can be created.

[0008]

However, in the above-mentioned conventional network synchronizer, as the number of digital lines 3 to 6 connected to the public network 2 increases, the signal line of the network synchronization clock to be supplied to the network synchronization circuit 34. There was a problem that the number of Further, when the number of digital lines 3 to 6 is large, the line interface unit that supplies the network synchronization clock is limited in order to suppress an increase in the number of signal lines, so that when the line fails, the other normal operation is performed normally. There was a problem that the network could not be synchronized even though there was an internal line.

The present invention solves such a conventional problem. By effectively utilizing an empty time slot on the internal data bus, the network can be used regardless of the number of digital lines connected to the public network. To provide a network synchronizer that makes it possible to create a stable system clock that is synchronized with the network, as long as the number of signal lines of the network synchronization clock supplied to the synchronization circuit is constant and the circuit is operating normally. That is the purpose.

[0010]

In order to achieve the above object, the present invention is connected to a public network by a plurality of digital lines,
A device for reproducing network synchronization timing from a plurality of lines, a means for transmitting a slot number in the network synchronization device pre-allocated to the same time slot of the same data bus in the device, and a bit for the slot number in the time slot. The network synchronization clock is regenerated from the line when the self-transmitted slot number matches the slot number monitored from the time slot.

[0011]

According to the present invention constructed as described above, the automatic switching of a plurality of network synchronization clocks to the network synchronization circuit is carried out by the hardware, regardless of the number of digital lines connected to the public network. Instead, the number of signal lines of the network synchronization clock supplied to the network synchronization circuit can be made constant.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

An example of the connection between the exchange and the public network via a plurality of digital lines is the same as that shown in FIG. 4, and the description thereof will be omitted.

FIG. 1 is a block diagram of the line interface unit of the exchange used in the network synchronizer according to the embodiment of the present invention in accordance with the connection example of FIG. In FIG. 1, reference numeral 12 denotes a frame assembling / disassembling unit, which is connected to the digital lines 3, 4, 5 or 6 and is connected to the digital line 3
Assembling and disassembling of the frame according to the types of ~ 6.
A unit control unit 13 controls the entire line interface unit and communicates with the central control unit inside the exchange 1. Reference numeral 14 is an internal data bus interface unit, and information such as voice data on the digital lines 3 to 6 is connected to the internal data bus of the exchange 1 by this block. 1
Reference numeral 7 is a network synchronization clock reproducing unit which reproduces a clock synchronized with the network from the line data received by the frame assembling / disassembling unit 12. This reproduced clock becomes a reference input clock of the network synchronization circuit 20 in the exchange 1.

Numeral 15 is a slot number insertion / monitor unit, which is located in the network synchronization line selection time slot defined in the empty time slot on the internal data bus and in the slot in which the line interface units 8 to 11 are inserted in the exchange 1. At the same time as sending the corresponding slot number, the time slot is monitored for each bit. However, at the time of line failure, regardless of the assigned slot number,
All "1" is sent to the network synchronization line selection time slot. The slot number insertion / monitor unit 15 monitors the network synchronization line selection time slot bit by bit, and when the monitor result matches the self insertion slot number, turns the network synchronization clock on / off control unit 16 on. , A network synchronization clock is supplied to the network synchronization circuit. On the other hand, when the numbers do not match, the network synchronization clock on / off control unit 16 is turned off to stop the supply of the network synchronization clock to the network synchronization circuit.

FIG. 3 shows an example of time slot allocation of the internal data bus of the exchange used in the network synchronizer in one embodiment of the present invention according to the connection example of FIG. The internal data bus has a bit timing clock of 2 MHz and a repetition frequency of 8 KHz, and 32 channels corresponding to 64 Kbps are multiplexed. In this example, TS0-T
Three ISDN basic interface B channels are allocated to S5, and one I channel is allocated to TS6 to TS28.
The B channel of the SDN primary rate interface is allocated. TS31 is defined as a network synchronization circuit selection time slot, and TS29 to TS30 are empty channels.

Next, an example of output control of the network synchronization clock in one embodiment of the present invention will be described with reference to FIG. In FIG. 3, 19 is a time switch.
Exchange connection of each time slot on the internal data bus 21 is performed. However, only the TS31 defined as the network synchronization circuit selection time slot is always connected back to the same data bus. Each of the line interface units 8, 9, 10 and 11 in the exchange 1 inserts a slot number corresponding to a slot inserted in the exchange 1 into a slot number /
It is sent to the TS 31 via the monitor unit 15. The slot numbers sent from the line interface units 8 to 11 are “wired-OR” on the TS 31 and are returned by the time switch 19. TS that has been folded back
31 is monitored by the slot number insertion / monitoring unit 15 of each of the line interface units 8 to 11, and is compared with the own transmission slot number for each bit. The line interface units 8 to 11 having the same comparison result for each bit turn on the network synchronization clock on / off control unit 16 in its own block.
and the network synchronization clock is supplied to the network synchronization circuit 20. If the comparison result for each bit does not match, the network synchronization clock on / off control unit 16 in its own block is turned on immediately when the bit comparison mismatch occurs.
Then, the supply of the network synchronization clock to the network synchronization circuit 20 is stopped.

In the example shown in FIG. 3, the slot numbers are # 0 to # 0.
Since it is # 3, the result of "wired OR"
Only the line interface units 8 to 11 having the slot number # 0 supply the network synchronization clock to the network synchronization circuit 20. Also, the line interface unit 8 in which the line failure has occurred
Since ~ 11 sends all "1" to TS31,
As a result of the "wired-OR", the monitor result and the self-sending slot number always conflict with each other, and thus it is possible to prevent synchronization pull-in due to an illegal clock.

Thus, according to the above embodiment, the public network 2
Irrespective of the number of digital lines 3-6 connected to
With the number of signal lines of the network synchronization clock supplied to the network synchronization circuit 20 being constant, it is possible to always create a stable system clock synchronized with the network as long as there is a line in normal operation.

[0020]

As described above, according to the present invention, the control of the clock supply to the network synchronizing circuit is autonomously executed in each line interface section by a simple method, so that it is connected to the public network. Regardless of the number of digital lines, the number of signal lines of the network synchronization clock supplied to the network synchronization circuit is constant, and as long as there are lines in normal operation, it is possible to always create a stable system clock synchronized with the network. .

Further, it is possible to omit the clock selection circuit which is conventionally required in the network synchronization circuit and which network synchronization clock is used as the input clock.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a line interface unit used in a network synchronization device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of time slot allocation used in the network synchronizer in one embodiment of the present invention.

FIG. 3 is a schematic block diagram for explaining network synchronization clock output control used in the network synchronization device in one embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing an example of connection between an exchange and a public network via a plurality of digital lines.

FIG. 5 is a schematic block diagram showing a line interface unit used in a conventional network synchronizer.

FIG. 6 is an explanatory diagram of an example of time slot allocation used in a conventional network synchronizer.

FIG. 7 is a schematic block diagram for explaining network synchronization clock output control used in a conventional network synchronization device.

[Explanation of symbols]

 1 Switch 2 Public Network 3 ISDN Basic Interface Line 4 ISDN Basic Interface Line 5 ISDN Basic Interface Line 6 ISDN Primary Rate Interface Line 8 Line Interface Unit 9 Line Interface Unit 10 Line Interface Unit 11 Line Interface Unit 12 Frame Assembly / Disassembly Unit 13 Unit control unit 14 Internal data bus interface unit 15 Slot number insertion / monitor unit 16 Network synchronization clock on / off control unit 17 Network synchronization clock recovery unit 19 Time switch 20 Network synchronization circuit 21 Internal data bus

Claims (1)

[Claims] 1. A slot number in a network synchronization device, which is connected to a public network by a plurality of digital lines and reproduces a network synchronization timing from the plurality of lines, which is pre-allocated to the same time slot of the same data bus in the device. And a means for monitoring the slot number in the time slot for each bit, and when the self-transmitted slot number and the slot number monitored from the time slot match, the network synchronization clock is regenerated from the line. A network synchronizer configured to.