JPS55135928A - Interruption processing system - Google Patents

Interruption processing system

Info

Publication number
JPS55135928A
JPS55135928A JP4391979A JP4391979A JPS55135928A JP S55135928 A JPS55135928 A JP S55135928A JP 4391979 A JP4391979 A JP 4391979A JP 4391979 A JP4391979 A JP 4391979A JP S55135928 A JPS55135928 A JP S55135928A
Authority
JP
Japan
Prior art keywords
interruption
cpu
latch
signal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4391979A
Other languages
Japanese (ja)
Inventor
Hiroshi Ino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4391979A priority Critical patent/JPS55135928A/en
Publication of JPS55135928A publication Critical patent/JPS55135928A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To make it possible to reduce the amount of hardware which is necessary for interruption processing, by resetting the interruption factor latches separately only in case the interruption factors have been read by CPU.
CONSTITUTION: When an interruption factor INT1 has been caused, an interruption factor latch 1 is set, and an interruption request signal INTRQ is is sent out to CPU. When CPU has received this signal, a read strobe signal STB is set. This signal STB is input to the interruption factor delay latch 3 and the AND gate 5. In accordance with an input of this signal STB, a setting output from the latch in which an interruption factor has been caused, among the interruption factors INT1WINTN, is set to the latch 3. And while CPU is in the course of read, the output of the latch 3 is output as an interruption factor status signal INTS. On the other hand, in case a timing signal TM has been input to the AND gate 5 while CPU is in the course of read, AND with the signal STB is taken, and those which have taken AND with signals INTS1WSN by the gates 6 and 7 reset the latches 1 and 2.
COPYRIGHT: (C)1980,JPO&Japio
JP4391979A 1979-04-11 1979-04-11 Interruption processing system Pending JPS55135928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4391979A JPS55135928A (en) 1979-04-11 1979-04-11 Interruption processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4391979A JPS55135928A (en) 1979-04-11 1979-04-11 Interruption processing system

Publications (1)

Publication Number Publication Date
JPS55135928A true JPS55135928A (en) 1980-10-23

Family

ID=12677115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4391979A Pending JPS55135928A (en) 1979-04-11 1979-04-11 Interruption processing system

Country Status (1)

Country Link
JP (1) JPS55135928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174725A (en) * 1981-04-20 1982-10-27 Hitachi Ltd Interruption controlling system
JPS5892024A (en) * 1981-11-17 1983-06-01 シ−メンス・アクチエンゲゼルシヤフト Method and apparatus for controlling interface between systems

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174725A (en) * 1981-04-20 1982-10-27 Hitachi Ltd Interruption controlling system
JPS5892024A (en) * 1981-11-17 1983-06-01 シ−メンス・アクチエンゲゼルシヤフト Method and apparatus for controlling interface between systems
JPH035622B2 (en) * 1981-11-17 1991-01-28 Siemens Ag

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