JPS5570059A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5570059A
JPS5570059A JP14444478A JP14444478A JPS5570059A JP S5570059 A JPS5570059 A JP S5570059A JP 14444478 A JP14444478 A JP 14444478A JP 14444478 A JP14444478 A JP 14444478A JP S5570059 A JPS5570059 A JP S5570059A
Authority
JP
Japan
Prior art keywords
layer
poly
condenser
dummy
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14444478A
Other languages
Japanese (ja)
Inventor
Kazuhiro Shimotori
Yasuharu Nagayama
Hideyuki Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14444478A priority Critical patent/JPS5570059A/en
Publication of JPS5570059A publication Critical patent/JPS5570059A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To eliminate the unbalance of the reading of 0 and 1, by forming a one transistor-dynamic RAM by means of two layer poly Si, by making up a one layer portion as a condenser electrode and a two layer portion as a gate electrode in a memory and by turning the layer portions the other way in dummy. CONSTITUTION:In a memory cell of a 1MIST+IC dynamic RAM, an n-type bit wire 13 is mounted to a p<->-type substrate 11, the first layer poly Si15 is installed through a thin SiO2 film 14' and used as a condenser electrode and the second layer poly Si16 is disposed onto a SiO2 film 14'' and employed as a gate electrode. In a dummy cell, meanwhile, a n-type bit wire 33 is mounted to a p<->-type substrate 31, the first layer poly Si35, 35' are installed through thin SiO2 films 34'', 34''' and used as gate electrodes and the second poly Si36 is disposed through a SiO2 film 34' and employed as a condenser electrode. Thus, the dummy condenser is easily formed, and the information of 0 and 1 memorized in the memory cell can stably be sensed and can be amplified.
JP14444478A 1978-11-20 1978-11-20 Semiconductor memory device Pending JPS5570059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14444478A JPS5570059A (en) 1978-11-20 1978-11-20 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14444478A JPS5570059A (en) 1978-11-20 1978-11-20 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5570059A true JPS5570059A (en) 1980-05-27

Family

ID=15362355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14444478A Pending JPS5570059A (en) 1978-11-20 1978-11-20 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5570059A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595662A (en) * 1982-07-01 1984-01-12 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595662A (en) * 1982-07-01 1984-01-12 Nec Corp Semiconductor device

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