JPS5568736A - Mis input protective circuit - Google Patents

Mis input protective circuit

Info

Publication number
JPS5568736A
JPS5568736A JP14239278A JP14239278A JPS5568736A JP S5568736 A JPS5568736 A JP S5568736A JP 14239278 A JP14239278 A JP 14239278A JP 14239278 A JP14239278 A JP 14239278A JP S5568736 A JPS5568736 A JP S5568736A
Authority
JP
Japan
Prior art keywords
destruction
clamping
misfet
prevent
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14239278A
Other languages
Japanese (ja)
Inventor
Kenjiro Yasunari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14239278A priority Critical patent/JPS5568736A/en
Publication of JPS5568736A publication Critical patent/JPS5568736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent the destruction of the gate information for the input MISFET by lowering the absolute value of the threshold voltage for clamping MISFET to prevent the transmission MISFET from being turned on. CONSTITUTION:The threshold level of clamping MISFETQ4 is set lower in terms of the absolute value than the threshold voltage of MISFETQ1-Q3 which constitute the normal logic circuit. And in case MISFETQ4 is the n-channel type, the n-type impurity is led into the channel region surface selectively through the gate insulator film. In this case, the clamping is given with the fixed voltage to the positive high voltage via the surface breakdown of FETQ4 and others in order to prevent the destruction. And in the case of the negative input voltage, the threshold voltage of FETQ4 is low. Thus transmission MISFETQ1 is not turned on, and as a result the destruction can be prevented for the gate information of input MISFETQ3.
JP14239278A 1978-11-20 1978-11-20 Mis input protective circuit Pending JPS5568736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14239278A JPS5568736A (en) 1978-11-20 1978-11-20 Mis input protective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14239278A JPS5568736A (en) 1978-11-20 1978-11-20 Mis input protective circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59176653A Division JPS60121820A (en) 1984-08-27 1984-08-27 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5568736A true JPS5568736A (en) 1980-05-23

Family

ID=15314286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14239278A Pending JPS5568736A (en) 1978-11-20 1978-11-20 Mis input protective circuit

Country Status (1)

Country Link
JP (1) JPS5568736A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2494040A1 (en) * 1980-11-07 1982-05-14 Hitachi Ltd DEVICE WITH INTEGRATED CIRCUITS WITH SEMICONDUCTORS PROTECTED AGAINST ACCIDENTAL OVERVOLTAGES
JPS6439118A (en) * 1987-08-04 1989-02-09 Nec Corp Gaas semiconductor integrated circuit
EP0323643A2 (en) * 1988-01-07 1989-07-12 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with a circuit limiting an input voltage to a predetermined voltage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127149A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127149A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2494040A1 (en) * 1980-11-07 1982-05-14 Hitachi Ltd DEVICE WITH INTEGRATED CIRCUITS WITH SEMICONDUCTORS PROTECTED AGAINST ACCIDENTAL OVERVOLTAGES
DE3144169A1 (en) * 1980-11-07 1982-07-22 Hitachi Microcomputer Engineering Ltd., Tokyo INTEGRATED SEMICONDUCTOR CIRCUIT
JPS6439118A (en) * 1987-08-04 1989-02-09 Nec Corp Gaas semiconductor integrated circuit
EP0323643A2 (en) * 1988-01-07 1989-07-12 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with a circuit limiting an input voltage to a predetermined voltage

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