JPS56118373A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS56118373A
JPS56118373A JP2240780A JP2240780A JPS56118373A JP S56118373 A JPS56118373 A JP S56118373A JP 2240780 A JP2240780 A JP 2240780A JP 2240780 A JP2240780 A JP 2240780A JP S56118373 A JPS56118373 A JP S56118373A
Authority
JP
Japan
Prior art keywords
input
voltage
increases
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2240780A
Other languages
Japanese (ja)
Inventor
Yasutaka Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP2240780A priority Critical patent/JPS56118373A/en
Publication of JPS56118373A publication Critical patent/JPS56118373A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Abstract

PURPOSE:To improve stability and precision of a circuit of an IC memory with floating gate type N channel FAMOS, by controlling in a proper way the writing time comparing some of the voltage of the input line to the input voltage. CONSTITUTION:35, 361...36N are MOS devices and 371-37N are n channel FAMOS devices. As the threshold voltage VTH increases because of the writing in the device 37, so the electric differential V38 increases at the point 38. Therefore comparing the V38 and the signals from D/A converting part 31, the input is suspended to turn the FET35 off when the change of the V38 (VTH) reaches the desired value. With such an arrangement, the scattering in the input to the device 37 is completely prevented, so that the operations with high precision and high resolution can be achieved.
JP2240780A 1980-02-25 1980-02-25 Semiconductor integrated circuit Pending JPS56118373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2240780A JPS56118373A (en) 1980-02-25 1980-02-25 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2240780A JPS56118373A (en) 1980-02-25 1980-02-25 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS56118373A true JPS56118373A (en) 1981-09-17

Family

ID=12081804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2240780A Pending JPS56118373A (en) 1980-02-25 1980-02-25 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS56118373A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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