JPS5565469A - Mos integrated circuit - Google Patents

Mos integrated circuit

Info

Publication number
JPS5565469A
JPS5565469A JP13952578A JP13952578A JPS5565469A JP S5565469 A JPS5565469 A JP S5565469A JP 13952578 A JP13952578 A JP 13952578A JP 13952578 A JP13952578 A JP 13952578A JP S5565469 A JPS5565469 A JP S5565469A
Authority
JP
Japan
Prior art keywords
layer
wiring
tolerance
variation
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13952578A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Minoru Takada
Yasushi Sato
Hiroshi Osanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13952578A priority Critical patent/JPS5565469A/en
Publication of JPS5565469A publication Critical patent/JPS5565469A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve protective function and also to increase conduction capacity by keeping a variation of tolerance between a semiconductor layer connected with wiring and a hole to connect wiring corresponding between a protective diode and an output stage MOSFET. CONSTITUTION:A p<+>-type source layer 33 and drain layer 34 are formed on an n-type substrate, and an n<+>-type source layer 35 and drain layer 36 of FET 32 are formed on P-well. The layers 33 and 35 are connected to power wirings 38, 40 respectively through holes 37 and 35. There is then arranged a common wiring 43 on gate insulating films 41, 42. The layers 34, 36 are connected with an output wiring 46 through holes 44, 45 in insulating film. A variation of tolerance l between the peripheral edge of the layer 34 and the hole 44 and a variation of tolerance l between the periphery of the layer 36 and the hole 45 are kept equal. According to this constitution, the dimension l is held similarly to an input protective diode, therefore a surging voltage can be relieved in good condition to a drain junction 49 to bring about no damage on the junction 49, thus coping with a large current.
JP13952578A 1978-11-13 1978-11-13 Mos integrated circuit Pending JPS5565469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13952578A JPS5565469A (en) 1978-11-13 1978-11-13 Mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13952578A JPS5565469A (en) 1978-11-13 1978-11-13 Mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5565469A true JPS5565469A (en) 1980-05-16

Family

ID=15247308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13952578A Pending JPS5565469A (en) 1978-11-13 1978-11-13 Mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5565469A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749272A (en) * 1980-09-09 1982-03-23 Matsushita Electric Ind Co Ltd Input protecting circuit
JPH07321318A (en) * 1984-06-06 1995-12-08 Texas Instr Inc <Ti> Protective device for semiconductor device
US5945700A (en) * 1996-07-24 1999-08-31 Nec Corporation Semiconductor device having a semiconductor switch structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749272A (en) * 1980-09-09 1982-03-23 Matsushita Electric Ind Co Ltd Input protecting circuit
JPH07321318A (en) * 1984-06-06 1995-12-08 Texas Instr Inc <Ti> Protective device for semiconductor device
US5945700A (en) * 1996-07-24 1999-08-31 Nec Corporation Semiconductor device having a semiconductor switch structure

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