JPS5548943A - Composite integrated circuit - Google Patents

Composite integrated circuit

Info

Publication number
JPS5548943A
JPS5548943A JP12149978A JP12149978A JPS5548943A JP S5548943 A JPS5548943 A JP S5548943A JP 12149978 A JP12149978 A JP 12149978A JP 12149978 A JP12149978 A JP 12149978A JP S5548943 A JPS5548943 A JP S5548943A
Authority
JP
Japan
Prior art keywords
chip
conductor
adhesive
dam
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12149978A
Other languages
Japanese (ja)
Inventor
Kazuo Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12149978A priority Critical patent/JPS5548943A/en
Publication of JPS5548943A publication Critical patent/JPS5548943A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors

Landscapes

  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE: To increase bonding strength, by providing a projected dam made of a conductor or dielectic body at the position for fitting a chip on a base at the time of fixing a semiconductor chip on an insulated base and pasting a chip to this with adhesive agent.
CONSTITUTION: Conductor 3 is fitted in the center of insulated base 1 corresponding to semiconductor chip 5 to be pasted later. On both sides of this are fited external electrode conductors 2. Next, chip 5 is fixed on conductor 3 by using adhesive 4. At this time, however, dam 9, made of a conductor or dielectric and having a uniform height, is built at the end part of conductor 3 so as to surround adhesive 4. Subsequently, chip 5 is fixed by means of adhesive 4, and two bonding pads 6 provided on chip 5 are respectively bonded to conductors 2 by means of wire 7. By this, no deterioration occurs in the strength of wire tension, nor deviation appears.
COPYRIGHT: (C)1980,JPO&Japio
JP12149978A 1978-10-04 1978-10-04 Composite integrated circuit Pending JPS5548943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12149978A JPS5548943A (en) 1978-10-04 1978-10-04 Composite integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12149978A JPS5548943A (en) 1978-10-04 1978-10-04 Composite integrated circuit

Publications (1)

Publication Number Publication Date
JPS5548943A true JPS5548943A (en) 1980-04-08

Family

ID=14812683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12149978A Pending JPS5548943A (en) 1978-10-04 1978-10-04 Composite integrated circuit

Country Status (1)

Country Link
JP (1) JPS5548943A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812420A (en) * 1986-09-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of producing a semiconductor device having a light transparent window
US5489752A (en) * 1992-12-15 1996-02-06 Sgs-Thomson Microelectronics S.R.L. Process for dissipating heat from a semiconductor package
JPH08181166A (en) * 1994-12-22 1996-07-12 Ibiden Co Ltd Printed wiring board
KR100355744B1 (en) * 2000-10-25 2002-10-19 앰코 테크놀로지 코리아 주식회사 Semiconductor package structure
US6691406B2 (en) * 2000-05-01 2004-02-17 Micron Technology, Inc. Methods of die attachment for BOC and F/C surface mount
EP2555268A1 (en) * 2010-03-31 2013-02-06 NGK Insulators, Ltd. Electronic device
WO2023150521A3 (en) * 2022-02-03 2023-11-23 Ciena Corporation Enhanced thermal control of a hybrid chip assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011770A (en) * 1973-06-04 1975-02-06
JPS52673A (en) * 1975-06-16 1977-01-06 Chiyuuichi Miyake Squid luring hooks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5011770A (en) * 1973-06-04 1975-02-06
JPS52673A (en) * 1975-06-16 1977-01-06 Chiyuuichi Miyake Squid luring hooks

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812420A (en) * 1986-09-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of producing a semiconductor device having a light transparent window
US5590462A (en) * 1992-02-15 1997-01-07 Sgs-Thomson Microelectronics S.R.L. Process for dissipating heat from a semiconductor package
US5489752A (en) * 1992-12-15 1996-02-06 Sgs-Thomson Microelectronics S.R.L. Process for dissipating heat from a semiconductor package
JPH08181166A (en) * 1994-12-22 1996-07-12 Ibiden Co Ltd Printed wiring board
US6691406B2 (en) * 2000-05-01 2004-02-17 Micron Technology, Inc. Methods of die attachment for BOC and F/C surface mount
KR100355744B1 (en) * 2000-10-25 2002-10-19 앰코 테크놀로지 코리아 주식회사 Semiconductor package structure
EP2555268A1 (en) * 2010-03-31 2013-02-06 NGK Insulators, Ltd. Electronic device
EP2555268A4 (en) * 2010-03-31 2014-06-18 Ngk Insulators Ltd Electronic device
WO2023150521A3 (en) * 2022-02-03 2023-11-23 Ciena Corporation Enhanced thermal control of a hybrid chip assembly

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