JPH08181166A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH08181166A JPH08181166A JP6336128A JP33612894A JPH08181166A JP H08181166 A JPH08181166 A JP H08181166A JP 6336128 A JP6336128 A JP 6336128A JP 33612894 A JP33612894 A JP 33612894A JP H08181166 A JPH08181166 A JP H08181166A
- Authority
- JP
- Japan
- Prior art keywords
- insulating
- pad
- wiring board
- printed wiring
- insulating pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32112—Disposition the layer connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，ボンディング用ワイヤ
ーの接続不良を防止することができる，プリント配線板
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board which can prevent defective connection of bonding wires.
【０００２】[0002]
【従来技術】従来，プリント配線板としては，図９に示
すごとく，基板６の表側面に形成したパターン回路５の
上に，電子部品搭載用の絶縁性パッド９を設けたものが
ある。絶縁性パッド９の上には，絶縁性接着剤２を介し
て，電子部品３が搭載されている。電子部品３は，絶縁
性パッド９の周囲に設けたボンディングパッド５０と，
ワイヤー３０を介して接続している。2. Description of the Related Art Conventionally, as a printed wiring board, there is one in which an insulating pad 9 for mounting an electronic component is provided on a pattern circuit 5 formed on a front surface of a substrate 6, as shown in FIG. The electronic component 3 is mounted on the insulating pad 9 via the insulating adhesive 2. The electronic component 3 includes a bonding pad 50 provided around the insulating pad 9,
It is connected via a wire 30.
【０００３】上記絶縁性パッド９は，ソルダーレジスト
を基板６の上に部分的に塗布することにより形成された
ものであり，電子部品３を搭載するためのダイパッドと
して用いられている。この絶縁性パッド９の下方には，
パターン回路５を設けることができ，基板６の表側面の
高密度実装化を図ることができる。The insulating pad 9 is formed by partially applying a solder resist on the substrate 6, and is used as a die pad for mounting the electronic component 3. Below this insulating pad 9,
The pattern circuit 5 can be provided, and high density mounting of the front surface of the substrate 6 can be achieved.
【０００４】[0004]
【解決しようとする課題】しかしながら，上記従来のプ
リント配線板においては，絶縁性パッド９の近くにボン
ディングパッド５０が位置している。そのため，絶縁性
接着剤２が絶縁性パッド９の側壁に沿って外周へと流出
し，ボンディングパッド５０を被覆する場合がある。こ
の場合には，ホンディングパッド５０とワイヤー３０と
の接続ができないおそれがある。However, in the above-mentioned conventional printed wiring board, the bonding pad 50 is located near the insulating pad 9. Therefore, the insulating adhesive 2 may flow out to the outer periphery along the side wall of the insulating pad 9 and cover the bonding pad 50. In this case, the bonding pad 50 and the wire 30 may not be connected.
【０００５】また，絶縁性接着剤２は，絶縁性パッド９
の外周へと流出するため，絶縁性接着剤２の厚みを制御
することが困難である。そのため，各プリント配線板毎
に電子部品３とボンディングパッド５０との高さ方向の
間隔が異なり，正確なワイヤーボンディングを行うこと
ができない。それ故，ワイヤー３０の接続不良を起こす
おそれがある。Further, the insulating adhesive 2 is used for the insulating pad 9
It is difficult to control the thickness of the insulating adhesive 2 because it flows out to the outer periphery of the. Therefore, the distance between the electronic component 3 and the bonding pad 50 in the height direction is different for each printed wiring board, and accurate wire bonding cannot be performed. Therefore, the connection of the wire 30 may be defective.
【０００６】本発明はかかる従来の問題点に鑑み，電子
部品接合用の絶縁性接着剤の流出がなく，ボンディング
用ワイヤーの接続不良を防止することができる，プリン
ト配線板を提供しようとするものである。In view of the above conventional problems, the present invention aims to provide a printed wiring board capable of preventing a defective connection of a bonding wire without the outflow of an insulating adhesive for joining electronic parts. Is.
【０００７】[0007]
【課題の解決手段】本発明は，基板に設けたパターン回
路の上に絶縁性パッドを設け，該絶縁性パッドの上に絶
縁性接着剤を介して電子部品を搭載し，該電子部品と上
記基板上に設けたボンディングパッドとの間をワイヤー
により接続する形式のプリント配線板において，上記絶
縁性パッドは，その周縁部に上記絶縁性接着剤の流出を
防止するための流出防止溝を有することを特徴とするプ
リント配線板にある。According to the present invention, an insulating pad is provided on a pattern circuit provided on a substrate, and an electronic component is mounted on the insulating pad via an insulating adhesive. In a printed wiring board of a type in which a wire is connected to a bonding pad provided on a substrate, the insulating pad has an outflow prevention groove at a peripheral portion thereof to prevent outflow of the insulating adhesive. The printed wiring board is characterized by.
【０００８】上記流出防止溝は，電子部品を搭載するた
めの絶縁性パッドにおいて，その周縁部に形成されてい
る。流出防止溝は，上記周縁部において，環状に形成さ
れていることが好ましい。これにより，絶縁性接着剤が
絶縁性パッドのいずれの方向に流動しても，そのすべて
が流出防止溝内に溜められる。そのため，絶縁性パッド
の外周に流出することを防止することができる。The outflow preventing groove is formed in the peripheral edge portion of the insulating pad for mounting the electronic component. The outflow prevention groove is preferably formed in an annular shape at the peripheral portion. As a result, even if the insulating adhesive flows in either direction of the insulating pad, all of the insulating adhesive is stored in the outflow prevention groove. Therefore, it can be prevented from flowing out to the outer periphery of the insulating pad.
【０００９】上記流出防止溝は，上記周縁部において，
環状に複数個形成することが好ましい。これにより，最
も内側の流出防止溝により絶縁性接着剤の流出がせき止
められ，更に流出した絶縁性接着剤はそれよりも外周の
流出防止溝によりせき止められる。環状の流出防止溝
は，そのコーナ部が曲線状に屈曲させてあることが好ま
しい。これにより，高い流出防止効果を得ることができ
る。The outflow prevention groove is provided in the peripheral edge portion.
It is preferable to form a plurality of rings. Thus, the innermost outflow prevention groove blocks the outflow of the insulating adhesive, and the inflowing insulating adhesive is further stopped by the outflow prevention groove on the outer periphery. The annular outflow prevention groove preferably has a curved corner portion. As a result, a high outflow prevention effect can be obtained.
【００１０】上記流出防止溝は，その深さが１０〜７０
μｍであることが好ましい。１０μｍ未満の場合には，
絶縁性接着剤が流出防止溝を越えて絶縁性パッドの外周
へと流出するおそれがある。一方，７０μｍを越える場
合には，流出防止溝を設ける絶縁性パッドの厚みが大き
くなり，プリント配線板の薄板化を妨げるおそれがあ
る。The outflow prevention groove has a depth of 10 to 70.
It is preferably μm. If it is less than 10 μm,
The insulative adhesive may flow over the outflow prevention groove to the outer periphery of the insulative pad. On the other hand, when the thickness exceeds 70 μm, the thickness of the insulating pad provided with the outflow prevention groove increases, which may hinder the thinning of the printed wiring board.
【００１１】上記流出防止溝は，その幅が５０〜３００
μｍであることが好ましい。５０μｍ未満の場合には，
絶縁性接着剤が流出防止溝を越えて絶縁性パッドの外周
へ流出するおそれがある。一方，３００μｍを越える場
合には，流出防止溝を設ける絶縁性パッドが大きくな
り，その周囲に設けるボンディングパッドと電子部品と
の距離が長くなり，正確なワイヤーボンドが困難となる
おそれがある。The width of the outflow prevention groove is 50 to 300.
It is preferably μm. If it is less than 50 μm,
The insulating adhesive may flow over the outflow prevention groove to the outer periphery of the insulative pad. On the other hand, when it exceeds 300 μm, the insulating pad provided with the outflow prevention groove becomes large, the distance between the bonding pad provided around it and the electronic component becomes long, and there is a possibility that accurate wire bonding becomes difficult.
【００１２】上記絶縁パッドの上面における流出防止溝
に囲まれた部分には，電子部品を搭載するための搭載部
が設けられている。該搭載部は，平坦状であることが好
ましい。これにより，電子部品の搭載を確実に行うこと
ができる。また，電子部品とボンディングパッドとの高
さ方向の間隔を制御することができ，両者の間を確実に
ワイヤーボンディングすることができる。上記流出防止
溝は，該流出防止溝の形成部分だけを残して，パターン
回路の上にソルダーレジストを塗布して，形成すること
ができる。A mounting portion for mounting an electronic component is provided in a portion surrounded by the outflow prevention groove on the upper surface of the insulating pad. The mounting portion is preferably flat. This makes it possible to reliably mount the electronic component. In addition, the distance between the electronic component and the bonding pad in the height direction can be controlled, and wire bonding can be reliably performed between the two. The outflow prevention groove can be formed by applying a solder resist on the pattern circuit, leaving only the formation portion of the outflow prevention groove.
【００１３】上記絶縁性パッドは，基板の表側面に設け
たパターン回路を被覆している。該パターン回路は，送
信用又は放熱用のいずれにも用いることができる。上記
絶縁性パッドの周囲には，ボンディングパッドを設けて
いる。上記絶縁性パッドは，例えば，ディスペンサによ
る，１回又は複数回の印刷により形成することができ
る。絶縁性パッドは，ソルダーレジスト等を用いて形成
ることができる。The insulating pad covers a pattern circuit provided on the front surface of the substrate. The pattern circuit can be used for either transmission or heat dissipation. A bonding pad is provided around the insulating pad. The insulating pad can be formed by printing once or a plurality of times with a dispenser, for example. The insulating pad can be formed by using a solder resist or the like.
【００１４】[0014]
【作用及び効果】本発明のプリント配線板においては，
絶縁性パッドの周縁部に，上記流出防止溝が設けられて
いる。この絶縁性パッドの上には，電子部品を搭載する
ために絶縁性接着剤が塗布される。このとき，絶縁性接
着剤が絶縁性パッドの周縁部に流動する。一方，絶縁性
パッドの周縁部には，凹状に窪んだ上記流出防止溝があ
る。In the printed wiring board of the present invention,
The outflow prevention groove is provided in the peripheral portion of the insulating pad. An insulating adhesive is applied on the insulating pad for mounting electronic components. At this time, the insulating adhesive flows to the peripheral portion of the insulating pad. On the other hand, the outflow-prevention groove that is recessed in the peripheral portion of the insulating pad is provided.
【００１５】そのため，絶縁性接着剤は，上記流出防止
溝の中に溜められ，絶縁性パッドの外周に流出すること
はない。従って，絶縁性パッドの外周に設けたボンディ
ングパッドが絶縁性接着剤により被覆されることはな
い。Therefore, the insulating adhesive is stored in the outflow prevention groove and does not flow out to the outer periphery of the insulating pad. Therefore, the bonding pad provided on the outer periphery of the insulating pad is not covered with the insulating adhesive.
【００１６】また，絶縁性接着剤は，流出防止溝により
せき止められるため，流出防止溝に囲まれた搭載部の全
体に均一な一定厚みの接着層が形成される。そのため，
基板と電子部品との高さ方向の間隔を制御することがで
きる。従って，電子部品とボンディングパッドとの間
を，正確にワイヤーボンディングすることができる。Further, since the insulating adhesive is dammed by the outflow prevention groove, an adhesive layer having a uniform thickness is formed on the entire mounting portion surrounded by the outflow prevention groove. for that reason,
It is possible to control the distance between the substrate and the electronic component in the height direction. Therefore, the wire bonding can be accurately performed between the electronic component and the bonding pad.
【００１７】本発明によれば，電子部品接合用の絶縁性
接着剤の流出がなく，ボンディング用ワイヤーの接続不
良を防止することができる，プリント配線板を提供する
ことができる。According to the present invention, it is possible to provide a printed wiring board in which an insulating adhesive for joining electronic components does not flow out and a connection failure of a bonding wire can be prevented.
【００１８】[0018]
実施例１ 本発明の実施例に係るプリント配線板について，図１〜
図６を用いて説明する。本例のプリント配線板１００
は，図１に示すごとく，絶縁性の基板６に設けたパター
ン回路５の上に絶縁性パッド１を設けている。絶縁性パ
ッド１の上には，絶縁性接着剤２を介して電子部品３が
搭載されている。電子部品３は，基板６の上に設けたボ
ンディングパッド５０との間を，ワイヤー３０により接
続されている。Example 1 A printed wiring board according to an example of the present invention is shown in FIGS.
This will be described with reference to FIG. Printed wiring board 100 of this example
As shown in FIG. 1, the insulating pad 1 is provided on the pattern circuit 5 provided on the insulating substrate 6. An electronic component 3 is mounted on the insulating pad 1 via an insulating adhesive 2. The electronic component 3 is connected to the bonding pad 50 provided on the substrate 6 by the wire 30.
【００１９】絶縁性パッド１の周縁部には，絶縁性接着
剤２の流出を防止するための環状の流出防止溝１１を有
している。流出防止溝１１は，図２に示すごとく，絶縁
性パッド１と同一の四角形状であり，そのコーナー部１
１０は，曲線状に屈曲させてある。流出防止溝１１は，
その深さが４０μｍであり，その幅が０．５ｍｍであ
る。An annular outflow prevention groove 11 for preventing outflow of the insulative adhesive 2 is provided in the peripheral portion of the insulative pad 1. As shown in FIG. 2, the outflow prevention groove 11 has the same rectangular shape as that of the insulating pad 1, and its corner portion 1
10 is bent in a curved shape. The outflow prevention groove 11 is
Its depth is 40 μm and its width is 0.5 mm.
【００２０】絶縁性パッド１の下には，図３に示すごと
く，パターン回路５が設けられている。また，絶縁性パ
ッド１の周囲には，ボンディングパッド５０が設けられ
ている。ボンディングパッド５０は，パターン回路５を
介して，基板６の側面に設けられた側面スルーホール５
５，又は基板６を貫通するスルーホール５３と接続して
いる。また，基板６の裏側面には，図１に示すごとく，
側面スルーホール５５と接続する実装用パッド５９が設
けられている。Below the insulating pad 1, a pattern circuit 5 is provided as shown in FIG. A bonding pad 50 is provided around the insulating pad 1. The bonding pad 50 is provided on the side surface of the substrate 6 via the side surface through hole 5 via the pattern circuit 5.
5, or is connected to a through hole 53 penetrating the substrate 6. On the back side of the substrate 6, as shown in FIG.
A mounting pad 59 connected to the side surface through hole 55 is provided.
【００２１】次に，上記プリント配線板１００の製造方
法について，図１，図４〜図６を用いて説明する。ま
ず，図４に示すごとく，基板６の表側面にはパターン回
路５及びボンディングパッド５０を，その側面には側面
スルーホール５５を，その裏側面には実装用パッド５９
を形成する。また，基板６を貫通するスルーホールを形
成する。Next, a method of manufacturing the printed wiring board 100 will be described with reference to FIGS. 1 and 4 to 6. First, as shown in FIG. 4, the pattern circuit 5 and the bonding pad 50 are provided on the front surface of the substrate 6, the side through hole 55 is provided on the side surface thereof, and the mounting pad 59 is provided on the back surface thereof.
To form. In addition, a through hole penetrating the substrate 6 is formed.
【００２２】次に，図５に示すごとく，パターン回路５
の間に，ソルダーレジスト１０１を印刷する。印刷はデ
ィスペンサを用いて行い，その印刷表面がパターン回路
５の表面と略同一面となるように平坦に印刷し，硬化さ
せる。Next, as shown in FIG. 5, the pattern circuit 5
In the meantime, the solder resist 101 is printed. Printing is performed using a dispenser, and the surface is printed flat so that the printed surface is substantially the same surface as the surface of the pattern circuit 5, and is cured.
【００２３】次に，図６に示すごとく，流出防止溝１１
の形成部分を除いて，硬化した上記ソルダーレジスト１
０１の上に，更にソルダーレジスト１０２を印刷する。
印刷厚みは４０μｍとし，その表面は平坦状とする。次
に，ソルダーレジスト１０２を硬化させて，流出防止溝
１１を有する絶縁性パッド１を形成する。Next, as shown in FIG. 6, the outflow prevention groove 11
Hardened solder resist 1 except for the formation part of
The solder resist 102 is further printed on 01.
The printing thickness is 40 μm and the surface is flat. Next, the solder resist 102 is cured to form the insulating pad 1 having the outflow prevention groove 11.
【００２４】次に，図１に示すごとく，絶縁性パッド１
の流出防止溝１１に囲まれた搭載部１２の上に，一定量
の絶縁性接着剤２を塗布する。次いで，絶縁性接着剤２
を介して電子部品３を搭載し，絶縁性パッド１の搭載部
１２に接着，固定する。次いで，電子部品３とボンディ
ングパッド５０との間を，ワイヤー３０により接続す
る。これにより，上記プリント配線板１００が得られ
る。Next, as shown in FIG. 1, the insulating pad 1
A fixed amount of the insulating adhesive 2 is applied on the mounting portion 12 surrounded by the outflow prevention groove 11. Next, insulating adhesive 2
The electronic component 3 is mounted via the, and is bonded and fixed to the mounting portion 12 of the insulating pad 1. Next, the electronic component 3 and the bonding pad 50 are connected by the wire 30. As a result, the printed wiring board 100 is obtained.
【００２５】次に，本例の作用効果について説明する。
本例のプリント配線板１００においては，図１に示すご
とく，電子部品３を搭載するに当たり，絶縁性接着剤２
が塗布される。このとき，絶縁性接着剤２が絶縁性パッ
ド１の周縁部に流動する。しかし，絶縁性パッド１の周
縁部には，図２に示すごとく，凹状に窪んだ流出防止溝
１１がある。更に，流出防止溝１１は環状である。その
ため，絶縁性接着剤２が絶縁性パッド１のいずれの方向
に流動しても，そのすべてが流出防止溝１１内に溜めら
れる。そのため，絶縁性接着剤２は，絶縁性パッド１の
外周に流出することがなく，ボンディングパッド５０が
絶縁性接着剤２により被覆されることはない。Next, the function and effect of this example will be described.
In the printed wiring board 100 of this example, as shown in FIG. 1, when mounting the electronic component 3, the insulating adhesive 2
Is applied. At this time, the insulating adhesive 2 flows to the peripheral portion of the insulating pad 1. However, in the peripheral portion of the insulating pad 1, as shown in FIG. Furthermore, the outflow prevention groove 11 is annular. Therefore, even if the insulating adhesive 2 flows in any direction of the insulating pad 1, all of the insulating adhesive 2 is accumulated in the outflow prevention groove 11. Therefore, the insulating adhesive 2 does not flow out to the outer periphery of the insulating pad 1, and the bonding pad 50 is not covered with the insulating adhesive 2.
【００２６】また，絶縁性接着剤２は，流出防止溝１１
によりせき止められるため，流出防止溝１１に囲まれた
搭載部１２の全体に一定で均一な厚みの接着層が形成さ
れる。そのため，基板６と電子部品３との高さ方向の間
隔を制御することができる。従って，電子部品３とボン
ディングパッド５０との間を，正確にワイヤーボンディ
ングすることができる。また，絶縁性パッド１の下に
は，パターン回路５が形成されている。そのため，プリ
ント配線板１００の表側面を有効に利用することがで
き，高密度実装化を図ることができる。In addition, the insulating adhesive 2 is provided in the outflow prevention groove 11
Since it is dammed down by the above, an adhesive layer having a constant and uniform thickness is formed on the entire mounting portion 12 surrounded by the outflow prevention groove 11. Therefore, the distance between the board 6 and the electronic component 3 in the height direction can be controlled. Therefore, the wire bonding can be accurately performed between the electronic component 3 and the bonding pad 50. A pattern circuit 5 is formed under the insulating pad 1. Therefore, the front surface of the printed wiring board 100 can be effectively used, and high-density mounting can be achieved.
【００２７】実施例２ 本例のプリント配線板１００においては，図７，図８に
示すごとく，絶縁性パッド１０において，その周縁部
に，２重の流出防止溝１１１，１１２が形成されてい
る。流出防止溝１１１，１１２は，図８に示すごとく，
絶縁性パッド１０と同一の四角形状であり，そのコーナ
ー部１１０，１２０は曲線状に屈曲させてある。絶縁性
パッド１０の上において，内側の流出防止溝１１２に囲
まれた搭載部１２には，絶縁性接着剤２を介して電子部
品３が搭載されている。その他は，実施例１と同様であ
る。Embodiment 2 In the printed wiring board 100 of this embodiment, as shown in FIGS. 7 and 8, in the insulating pad 10, double outflow preventing grooves 111 and 112 are formed in the peripheral portion thereof. . The outflow prevention grooves 111 and 112 are, as shown in FIG.
It has the same rectangular shape as the insulating pad 10, and its corner portions 110 and 120 are bent in a curved shape. On the insulating pad 10, the electronic component 3 is mounted on the mounting portion 12 surrounded by the inside outflow prevention groove 112 via the insulating adhesive 2. Others are the same as in the first embodiment.
【００２８】本例においては，内側の流出防止溝１１２
により絶縁性接着剤２がせき止められる。そのため，内
側の流出防止溝１１２により絶縁性接着剤２の流出がせ
き止められ，万が一絶縁性接着剤２が流出した場合にも
外側の流出防止溝１１１により完全にせき止めることが
できる。その他，本例においても実施例１と同様の効果
を得ることができる。In this example, the inner outflow prevention groove 112
Thus, the insulating adhesive 2 is dammed up. Therefore, the outflow prevention groove 112 on the inner side prevents the insulative adhesive 2 from flowing out, and even if the insulative adhesive 2 flows out, the outflow prevention groove 111 on the outer side can completely prevent the outflow. In addition, in this example, the same effect as that of the first embodiment can be obtained.
【図１】実施例１のプリント配線板の断面図。FIG. 1 is a sectional view of a printed wiring board according to a first embodiment.
【図２】実施例１の絶縁性パッドの形状を示す説明図。FIG. 2 is an explanatory view showing the shape of an insulating pad of Example 1.
【図３】実施例１の，基板の表側面に設けたパターン回
路と絶縁性パッドとの配置関係を示す，プリント配線板
の平面図。FIG. 3 is a plan view of the printed wiring board showing the positional relationship between the pattern circuit provided on the front surface of the substrate and the insulating pad according to the first embodiment.
【図４】実施例１のプリント配線板の製造方法におい
て，パターン回路等を形成した基板の断面図。FIG. 4 is a cross-sectional view of a substrate on which a pattern circuit and the like are formed in the printed wiring board manufacturing method according to the first embodiment.
【図５】図４に続く，絶縁性パッド用ソルダーレジスト
の第１回目印刷後の基板の断面図。FIG. 5 is a cross-sectional view of the substrate after the first printing of the insulating pad solder resist, following FIG. 4;
【図６】図５に続く，絶縁性パッド用ソルダーレジスト
の第２回目印刷後の基板の断面図。FIG. 6 is a cross-sectional view of the substrate after the second printing of the insulating pad solder resist, following FIG. 5;
【図７】実施例２のプリント配線板の断面図。FIG. 7 is a cross-sectional view of the printed wiring board of Example 2.
【図８】実施例２の，絶縁性パッドの形状を示す説明
図。FIG. 8 is an explanatory view showing the shape of an insulating pad according to the second embodiment.
【図９】従来例のプリント配線板の断面図。FIG. 9 is a cross-sectional view of a conventional printed wiring board.
１，１０．．．絶縁性パッド， １００．．．プリント配線板， １１，１１１，１１２．．．流出防止溝， １２．．．搭載部， ２．．．絶縁性接着剤， ３．．．電子部品， ３０．．．ワイヤー， ５．．．パターン回路， ５０．．．ボンディングパッド， ６．．．基板， 1,10. . . Insulating pad, 100. . . Printed wiring board, 11, 111, 112. . . Outflow prevention groove, 12. . . Mounting part, 2. . . Insulating adhesive, 3. . . Electronic components, 30. . . Wire, 5. . . Pattern circuit, 50. . . Bonding pad, 6. . . substrate,
Claims (6)
パッドを設け，該絶縁性パッドの上に絶縁性接着剤を介
して電子部品を搭載し，該電子部品と上記基板上に設け
たボンディングパッドとの間をワイヤーにより接続する
形式のプリント配線板において，上記絶縁性パッドは，
その周縁部に上記絶縁性接着剤の流出を防止するための
流出防止溝を有することを特徴とするプリント配線板。1. An insulating pad is provided on a pattern circuit provided on a substrate, an electronic component is mounted on the insulating pad via an insulating adhesive, and the electronic component and the substrate are provided with the electronic component. In a printed wiring board of the type in which a wire is connected to the bonding pad, the insulating pad is
A printed wiring board having an outflow preventing groove for preventing outflow of the above-mentioned insulating adhesive at its peripheral portion.
環状に形成されていることを特徴とするプリント配線
板。2. The outflow prevention groove according to claim 1,
A printed wiring board, which is formed in an annular shape.
溝は，その深さが１０〜７０μｍであることを特徴とす
るプリント配線板。3. The printed wiring board according to claim 1, wherein the outflow prevention groove has a depth of 10 to 70 μm.
上記流出防止溝は，その幅が５０〜３００μｍであるこ
とを特徴とするプリント配線板。4. The method according to claim 1, wherein
The outflow prevention groove has a width of 50 to 300 μm.
上記流出防止溝に囲まれた絶縁性パッドの上には，電子
部品を搭載するための平坦状の搭載部が設けられている
ことを特徴とするプリント配線板。5. The method according to any one of claims 1 to 4,
A printed wiring board, wherein a flat mounting portion for mounting an electronic component is provided on the insulating pad surrounded by the outflow prevention groove.
上記絶縁性パッドはソルダーレジストであることを特徴
とするプリント配線板。6. The method according to any one of claims 1 to 5,
The printed wiring board, wherein the insulating pad is a solder resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6336128A JPH08181166A (en) | 1994-12-22 | 1994-12-22 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6336128A JPH08181166A (en) | 1994-12-22 | 1994-12-22 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08181166A true JPH08181166A (en) | 1996-07-12 |
Family
ID=18295992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6336128A Pending JPH08181166A (en) | 1994-12-22 | 1994-12-22 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08181166A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6853089B2 (en) | 2001-09-18 | 2005-02-08 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| JP2006066551A (en) * | 2004-08-25 | 2006-03-09 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP2007012716A (en) * | 2005-06-28 | 2007-01-18 | Rohm Co Ltd | Semiconductor device |
| WO2010001505A1 (en) * | 2008-07-02 | 2010-01-07 | オムロン株式会社 | Electronic component |
| JP2011044720A (en) * | 2010-09-17 | 2011-03-03 | Rohm Co Ltd | Semiconductor device |
| JP2012049274A (en) * | 2010-08-26 | 2012-03-08 | Mitsubishi Electric Corp | Substrate support plate and method of bonding wafer temporarily to substrate support plate |
| JP2013254984A (en) * | 2013-08-23 | 2013-12-19 | Rohm Co Ltd | Semiconductor device |
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| JPS5548943A (en) * | 1978-10-04 | 1980-04-08 | Hitachi Ltd | Composite integrated circuit |
| JPS59143047U (en) * | 1983-03-14 | 1984-09-25 | 三菱電機株式会社 | circuit parts |
| JPS60114844U (en) * | 1984-01-10 | 1985-08-03 | 三菱電機株式会社 | thermal head |
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| JPS5548943A (en) * | 1978-10-04 | 1980-04-08 | Hitachi Ltd | Composite integrated circuit |
| JPS59143047U (en) * | 1983-03-14 | 1984-09-25 | 三菱電機株式会社 | circuit parts |
| JPS60114844U (en) * | 1984-01-10 | 1985-08-03 | 三菱電機株式会社 | thermal head |
| JPS6161833U (en) * | 1984-09-28 | 1986-04-25 | ||
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6853089B2 (en) | 2001-09-18 | 2005-02-08 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| KR100918745B1 (en) * | 2001-09-18 | 2009-09-24 | 가부시키가이샤 히타치세이사쿠쇼 | A semiconductor device and method of manufacturing the same |
| JP2006066551A (en) * | 2004-08-25 | 2006-03-09 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP4565931B2 (en) * | 2004-08-25 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2007012716A (en) * | 2005-06-28 | 2007-01-18 | Rohm Co Ltd | Semiconductor device |
| WO2010001505A1 (en) * | 2008-07-02 | 2010-01-07 | オムロン株式会社 | Electronic component |
| US8274797B2 (en) | 2008-07-02 | 2012-09-25 | Omron Corporation | Electronic component |
| JP2012049274A (en) * | 2010-08-26 | 2012-03-08 | Mitsubishi Electric Corp | Substrate support plate and method of bonding wafer temporarily to substrate support plate |
| JP2011044720A (en) * | 2010-09-17 | 2011-03-03 | Rohm Co Ltd | Semiconductor device |
| JP2013254984A (en) * | 2013-08-23 | 2013-12-19 | Rohm Co Ltd | Semiconductor device |
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