JPS554636A - Output controller - Google Patents

Output controller

Info

Publication number
JPS554636A
JPS554636A JP7742878A JP7742878A JPS554636A JP S554636 A JPS554636 A JP S554636A JP 7742878 A JP7742878 A JP 7742878A JP 7742878 A JP7742878 A JP 7742878A JP S554636 A JPS554636 A JP S554636A
Authority
JP
Japan
Prior art keywords
bit
information
gates
methods
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7742878A
Other languages
Japanese (ja)
Inventor
Takashi Abe
Kazuyoshi Osako
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7742878A priority Critical patent/JPS554636A/en
Publication of JPS554636A publication Critical patent/JPS554636A/en
Pending legal-status Critical Current

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  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To obtain an output controller which controls both one-bit information and multi-bit parallel information, by providing a one-bit information storing method, multi-bit writing method, 1st and 2nd gate methods, and gate control method.
CONSTITUTION: To store pieces of eight-bit parallel information D0 to D7 in eight one-bit information storing methods M0 to M7, switching signal LM is made logic "1" and output terminals C0 to C7 of decoder DEC1 are all made "1". As a result, 1st gates NA10 to NA17 and 2nd gates NA20 to NA27 close and multibit writing methods NA0 to NA7 open, so that pieces of information D0 to D7 will be inputted to storing methods M0 to M7. To store one-bit information, switching signal LM is made "0". Assuming that bit address signal BAD assigns storing method M1, only gate NA11 among 1st gates opens while others close and only NA21 among the 2nd gates closes while others open, so that one-bit information DA will be inputted to only storing method M1.
COPYRIGHT: (C)1980,JPO&Japio
JP7742878A 1978-06-28 1978-06-28 Output controller Pending JPS554636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7742878A JPS554636A (en) 1978-06-28 1978-06-28 Output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7742878A JPS554636A (en) 1978-06-28 1978-06-28 Output controller

Publications (1)

Publication Number Publication Date
JPS554636A true JPS554636A (en) 1980-01-14

Family

ID=13633709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7742878A Pending JPS554636A (en) 1978-06-28 1978-06-28 Output controller

Country Status (1)

Country Link
JP (1) JPS554636A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594008U (en) * 1982-06-29 1984-01-11 ソニ−・テクトロニクス株式会社 Analog circuit control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594008U (en) * 1982-06-29 1984-01-11 ソニ−・テクトロニクス株式会社 Analog circuit control device

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