JPS6481006A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS6481006A
JPS6481006A JP23812487A JP23812487A JPS6481006A JP S6481006 A JPS6481006 A JP S6481006A JP 23812487 A JP23812487 A JP 23812487A JP 23812487 A JP23812487 A JP 23812487A JP S6481006 A JPS6481006 A JP S6481006A
Authority
JP
Japan
Prior art keywords
register
instruction
common line
carried out
repetitively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23812487A
Other languages
Japanese (ja)
Inventor
Mikio Yonekura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP23812487A priority Critical patent/JPS6481006A/en
Publication of JPS6481006A publication Critical patent/JPS6481006A/en
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

PURPOSE:To carry out an instruction for common line control at a high speed by using a reset control means which resets forcibly and continuously a relay coil in accordance with the state of a common line. CONSTITUTION:The logic instructions of a ladder diagram stored in an instruction memory 1 are successively carried out by an arithmetic processor 10. When a common line control instruction is carried out, the designated bit data, i.e., a contact is read out of a data memory 2 and set at a bit register 18a. When the register 18a is set at zero, the address of a coil to be reset at a write address register 12 is set repetitively together with zero written repetitively into a data memory pointed by the register 12. While the next instruction is carried out as ordinary when the register 18a is set at one.
JP23812487A 1987-09-22 1987-09-22 Programmable controller Pending JPS6481006A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23812487A JPS6481006A (en) 1987-09-22 1987-09-22 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23812487A JPS6481006A (en) 1987-09-22 1987-09-22 Programmable controller

Publications (1)

Publication Number Publication Date
JPS6481006A true JPS6481006A (en) 1989-03-27

Family

ID=17025536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23812487A Pending JPS6481006A (en) 1987-09-22 1987-09-22 Programmable controller

Country Status (1)

Country Link
JP (1) JPS6481006A (en)

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