JPS5443638A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS5443638A
JPS5443638A JP10987477A JP10987477A JPS5443638A JP S5443638 A JPS5443638 A JP S5443638A JP 10987477 A JP10987477 A JP 10987477A JP 10987477 A JP10987477 A JP 10987477A JP S5443638 A JPS5443638 A JP S5443638A
Authority
JP
Japan
Prior art keywords
data
register
control
address
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10987477A
Other languages
Japanese (ja)
Inventor
Yoshinori Totsugi
Nobuhiro Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10987477A priority Critical patent/JPS5443638A/en
Publication of JPS5443638A publication Critical patent/JPS5443638A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize the reduced hardware and simplified control program by eliminating the need of a memory circuit for temporarily standby data and the control for standby reading, by constituting an address update device so that when read data is specific one, the address update of the memory unit is not done.
CONSTITUTION: Central processor 7 prepares for transmission data (a) in data storage area 1 of the memory unit, and then, sets the head address of the transmission data to data address register 2, thereby moving the control to communication controller 8. This controller 8 is provided with shift memory circuit 5, indentification register 3, circuit transmission register 4, and common control part 9' and register 3 indentifies under the control of control part 9' that read data is specific one, so that the update of the memory unit will not be done.
COPYRIGHT: (C)1979,JPO&Japio
JP10987477A 1977-09-14 1977-09-14 Communication controller Pending JPS5443638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10987477A JPS5443638A (en) 1977-09-14 1977-09-14 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10987477A JPS5443638A (en) 1977-09-14 1977-09-14 Communication controller

Publications (1)

Publication Number Publication Date
JPS5443638A true JPS5443638A (en) 1979-04-06

Family

ID=14521366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10987477A Pending JPS5443638A (en) 1977-09-14 1977-09-14 Communication controller

Country Status (1)

Country Link
JP (1) JPS5443638A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143434A (en) * 1974-05-02 1975-11-18
JPS50156331A (en) * 1974-06-05 1975-12-17

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50143434A (en) * 1974-05-02 1975-11-18
JPS50156331A (en) * 1974-06-05 1975-12-17

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