JPS5538040A - High-voltage-resisting semiconductor device - Google Patents

High-voltage-resisting semiconductor device

Info

Publication number
JPS5538040A
JPS5538040A JP11098678A JP11098678A JPS5538040A JP S5538040 A JPS5538040 A JP S5538040A JP 11098678 A JP11098678 A JP 11098678A JP 11098678 A JP11098678 A JP 11098678A JP S5538040 A JPS5538040 A JP S5538040A
Authority
JP
Japan
Prior art keywords
junction
base
voltage
opening
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11098678A
Other languages
Japanese (ja)
Inventor
Shigeru Ozawa
Takao Emoto
Yoshitaka Hara
Takashi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11098678A priority Critical patent/JPS5538040A/en
Publication of JPS5538040A publication Critical patent/JPS5538040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it easy to produce a device with high-voltage-resisting PN junction, by removing a part of the high impurity concentration on the surface of a unidirectional region of a semiconductor in a planer type semiconductor device.
CONSTITUTION: SiO2 film is provided on the surface of N-type silicon base 11, anda part of it is removed by the photo-etching method so as to form an opening. By diffusing boron, for example, from this opening, P-type layer 12 is formed. Next, by the photo-etching method, an opening is made on a part of SiO2 film on the main surface of base 11 which was formed when P-type layer 12 was formed, and electrode 14 is formed here. On the back of base 11 is fitted metal electrode 15. Further, by mechanical or electrochermical grinding, a part of base 11, including the PN junction is cut and thereby mesa surface 16 is formed. On mesa surface 16 is formed passivation layer 17. This can be generally applied to planer type semiconductor devices, and since the high impurity layer of the PN junction in the neighborhood of the surface is removed by this, it is possible to make the PN junction high-voltage resistant.
COPYRIGHT: (C)1980,JPO&Japio
JP11098678A 1978-09-09 1978-09-09 High-voltage-resisting semiconductor device Pending JPS5538040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11098678A JPS5538040A (en) 1978-09-09 1978-09-09 High-voltage-resisting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11098678A JPS5538040A (en) 1978-09-09 1978-09-09 High-voltage-resisting semiconductor device

Publications (1)

Publication Number Publication Date
JPS5538040A true JPS5538040A (en) 1980-03-17

Family

ID=14549499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11098678A Pending JPS5538040A (en) 1978-09-09 1978-09-09 High-voltage-resisting semiconductor device

Country Status (1)

Country Link
JP (1) JPS5538040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5321048A (en) * 1976-08-10 1978-02-27 Nippon Electric Co Constant current density plating device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5321048A (en) * 1976-08-10 1978-02-27 Nippon Electric Co Constant current density plating device

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