JPS55125671A - High withstand voltage semiconductor device - Google Patents

High withstand voltage semiconductor device

Info

Publication number
JPS55125671A
JPS55125671A JP3356679A JP3356679A JPS55125671A JP S55125671 A JPS55125671 A JP S55125671A JP 3356679 A JP3356679 A JP 3356679A JP 3356679 A JP3356679 A JP 3356679A JP S55125671 A JPS55125671 A JP S55125671A
Authority
JP
Japan
Prior art keywords
substrate
junction
region
type
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3356679A
Other languages
Japanese (ja)
Inventor
Takashi Suga
Tadaichi Murata
Chiharu Tsunoishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP3356679A priority Critical patent/JPS55125671A/en
Publication of JPS55125671A publication Critical patent/JPS55125671A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To provide a semiconductor device having high withstand voltage by forming a P-N junction in a semiconductor substrate, and reducing the thickness of the substrate at the periphery of the surface junction by utilizing an isolating groove for scribing the junction therearound after forming the P-N junction. CONSTITUTION:A mask of oxide film is formed on the back surface of an n-type silicon substrate, and two p<+>-type regions 2 are diffused to become thereafter scribe lines. Then, a mask of oxide film is similarly formed on the surface of the substrate, a p<+>-type region 3 is diffused to be connected to the region 2, p-type impurity is diffused in the entire surface without using the mask on the back surface of the substrate to form a p<+>-type layer 4, and the layer 4, the regions 2 and 3 are all connected as isolating grooves. When n<+>-type regions 5 are diffused on the front surface of the substrate to become a rectifier, the depth x of the region 3 is selected to be less than the thickness XN of the substrate 1 residued under the region 5, and the thickness of the substrate 1 is reduced at the surface edge surrounding the pn junction. Then, the central portion 6 of the region 3 is divided into element pellets as a scribe line from the substrate 1.
JP3356679A 1979-03-22 1979-03-22 High withstand voltage semiconductor device Pending JPS55125671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3356679A JPS55125671A (en) 1979-03-22 1979-03-22 High withstand voltage semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3356679A JPS55125671A (en) 1979-03-22 1979-03-22 High withstand voltage semiconductor device

Publications (1)

Publication Number Publication Date
JPS55125671A true JPS55125671A (en) 1980-09-27

Family

ID=12390086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3356679A Pending JPS55125671A (en) 1979-03-22 1979-03-22 High withstand voltage semiconductor device

Country Status (1)

Country Link
JP (1) JPS55125671A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265369A (en) * 1985-09-17 1987-03-24 Rohm Co Ltd Manufacture of bipolar transistor device with high dielectric strength
US7389813B2 (en) 1999-02-12 2008-06-24 Asml Holding N.V. Systems and methods for controlling local environment
CN100449790C (en) * 2004-03-30 2009-01-07 三垦电气株式会社 Semiconductor device and method of manufacture therefor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118359A (en) * 1973-03-12 1974-11-12
JPS50141978A (en) * 1974-05-02 1975-11-15
JPS5186976A (en) * 1975-01-29 1976-07-30 Hitachi Ltd KOTAIATSU HANDOTAISOCHINOSEIHO
JPS5193877A (en) * 1975-02-17 1976-08-17
JPS51129178A (en) * 1975-04-18 1976-11-10 Toshiba Corp Semiconductor
JPS5248469A (en) * 1975-10-15 1977-04-18 Matsushita Electric Ind Co Ltd Process for production of semiconductor device
JPS54112189A (en) * 1978-02-22 1979-09-01 Mitsubishi Electric Corp Mesa semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118359A (en) * 1973-03-12 1974-11-12
JPS50141978A (en) * 1974-05-02 1975-11-15
JPS5186976A (en) * 1975-01-29 1976-07-30 Hitachi Ltd KOTAIATSU HANDOTAISOCHINOSEIHO
JPS5193877A (en) * 1975-02-17 1976-08-17
JPS51129178A (en) * 1975-04-18 1976-11-10 Toshiba Corp Semiconductor
JPS5248469A (en) * 1975-10-15 1977-04-18 Matsushita Electric Ind Co Ltd Process for production of semiconductor device
JPS54112189A (en) * 1978-02-22 1979-09-01 Mitsubishi Electric Corp Mesa semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6265369A (en) * 1985-09-17 1987-03-24 Rohm Co Ltd Manufacture of bipolar transistor device with high dielectric strength
US7389813B2 (en) 1999-02-12 2008-06-24 Asml Holding N.V. Systems and methods for controlling local environment
CN100449790C (en) * 2004-03-30 2009-01-07 三垦电气株式会社 Semiconductor device and method of manufacture therefor
US7511316B2 (en) 2004-03-30 2009-03-31 Sanken Electric Co., Ltd. Semiconductor device resistive to high voltage and capable of controlling leakage current

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