JPS5534433A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5534433A
JPS5534433A JP10661278A JP10661278A JPS5534433A JP S5534433 A JPS5534433 A JP S5534433A JP 10661278 A JP10661278 A JP 10661278A JP 10661278 A JP10661278 A JP 10661278A JP S5534433 A JPS5534433 A JP S5534433A
Authority
JP
Japan
Prior art keywords
layers
mask
sio
spaces
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10661278A
Other languages
Japanese (ja)
Inventor
Mikio Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10661278A priority Critical patent/JPS5534433A/en
Publication of JPS5534433A publication Critical patent/JPS5534433A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To selectively mount diffused regions that mutual spaces are accurately set, by placing mask layers, which spaces are prescribed highly precise, on a semiconductor substrate, by forming layer containing impurities on the layers and by thermally treating these layers.
CONSTITUTION: Mask layers 12A and 12B that workability is excellent, the accuracy of etching is high and have mask effect to impurities are made up on a semiconductor substrate such as a P type Si substrate 11 at regular intervals by Si3N4. A layer 13 containing impurities, such as, B dope SiO2, etc. and an insulating layer 14, which does not contain impurities, such as, SiO2, etc., are successively built up on the layers. These insulating layers existing between the mask layers 12A, 12B are selectively removed, a thin insulating layer 16 of SiO2, etc. is formed on the substrate 11 exposed, and these layers are thermally treated, thus making up N type diffused layers 17 and 18, which spaces are prescribed by means of the mask layers. Consequently, this MOS device that the length of channels is decided highly precise can be prepared.
COPYRIGHT: (C)1980,JPO&Japio
JP10661278A 1978-08-31 1978-08-31 Preparation of semiconductor device Pending JPS5534433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10661278A JPS5534433A (en) 1978-08-31 1978-08-31 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10661278A JPS5534433A (en) 1978-08-31 1978-08-31 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5534433A true JPS5534433A (en) 1980-03-11

Family

ID=14437934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10661278A Pending JPS5534433A (en) 1978-08-31 1978-08-31 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5534433A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127180U (en) * 1984-07-20 1986-02-18 スタンレー電気株式会社 display device
JPS63115194A (en) * 1986-10-31 1988-05-19 日本精機株式会社 Display device
JPH0164687U (en) * 1987-10-20 1989-04-25

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6127180U (en) * 1984-07-20 1986-02-18 スタンレー電気株式会社 display device
JPS63115194A (en) * 1986-10-31 1988-05-19 日本精機株式会社 Display device
JPH0164687U (en) * 1987-10-20 1989-04-25

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