JPS5526682A - Semiconductor integrated circuit device provided with lateral transistor - Google Patents
Semiconductor integrated circuit device provided with lateral transistorInfo
- Publication number
- JPS5526682A JPS5526682A JP10023578A JP10023578A JPS5526682A JP S5526682 A JPS5526682 A JP S5526682A JP 10023578 A JP10023578 A JP 10023578A JP 10023578 A JP10023578 A JP 10023578A JP S5526682 A JPS5526682 A JP S5526682A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- density
- layer
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE: To improve fT, hFE and BVCBO by setting a density of the impurity at a low level and uniform in the vicinity of a collector and a maximum in the emitter side, by permitting an inclination in the vicinity of an emitter, in forming a base region.
CONSTITUTION: An N+-type buried region 12 and a P+-type buried region 13 surrounding it are formed in a Ptype Si substrate 11 to epitaxially-grow N-type layer 14 used for a base region over the full surface. Subsequently, a shallow P+- type insulation region 15 is provided in the layer 14 corresponding to the region 13 to be covered with a SiO2 film 15 over the full surface, and an opening 17 is given to a position corresponding to the region 12. Thereafter, in order to raise the density of a part of impurities in the base region, an N+-type region 18 is diffusion- formed to be heat-treated and as a result, the depth of the region 18 is increased and a region 5 is connected to the region 13. Subsequently, a P+-type emitter region 9 is diffusion-formed in the region 18 and a P+-type collector region 20 is provided in the layer 14 having a low density separated from the region 18. The base region 14 having the density difference is provided between the regions 19 and 20.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10023578A JPS5526682A (en) | 1978-08-16 | 1978-08-16 | Semiconductor integrated circuit device provided with lateral transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10023578A JPS5526682A (en) | 1978-08-16 | 1978-08-16 | Semiconductor integrated circuit device provided with lateral transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5526682A true JPS5526682A (en) | 1980-02-26 |
Family
ID=14268592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10023578A Pending JPS5526682A (en) | 1978-08-16 | 1978-08-16 | Semiconductor integrated circuit device provided with lateral transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5526682A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55137370U (en) * | 1980-04-02 | 1980-09-30 |
-
1978
- 1978-08-16 JP JP10023578A patent/JPS5526682A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55137370U (en) * | 1980-04-02 | 1980-09-30 |
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