JPS5522875A - Manufacturing method of semiconductor integrated circuit device with lateral transistor - Google Patents

Manufacturing method of semiconductor integrated circuit device with lateral transistor

Info

Publication number
JPS5522875A
JPS5522875A JP9689578A JP9689578A JPS5522875A JP S5522875 A JPS5522875 A JP S5522875A JP 9689578 A JP9689578 A JP 9689578A JP 9689578 A JP9689578 A JP 9689578A JP S5522875 A JPS5522875 A JP S5522875A
Authority
JP
Japan
Prior art keywords
layer
base layer
sio
lateral transistor
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9689578A
Other languages
Japanese (ja)
Inventor
Hiroshi Saikai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9689578A priority Critical patent/JPS5522875A/en
Publication of JPS5522875A publication Critical patent/JPS5522875A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To improve the various characteristics of a lateral transistor by forming a base layer having a high impurity density, adjacent to a collector layer by implanting an ion or diffusion with an opening provided in an Si3N4 film and further by forming an emitter layer in the base layer by a self-matching with an opening.
CONSTITUTION: An N-epi layer 14 on a P-type substrate 11 is separated by P+ layers 13 and 15. Openings 19 and 20 are provided for the lamination of an SiO2 16 and Si3N4 17 over an N+buried layer 12. An N+base layer 22 is formed by covering selectively with the SiO2 18, and buried under a high temperature condition. Next, the SiO2 18 is removed and a P+ type emitter 23 and a collector 24 are made by self-matching. The N+base layer of a lateral transistor obtained by such a process has a high accuracy and its impurity density becomes higher in the emitter region than in the collector region. Therefore, a resistance rbb is lowered and a BVCEO is increased because of non-occurrence of a punch-through even in the narrow base width. An hFE becomes great and an fT is also raised because an accelerating field may be formed in the base layer.
COPYRIGHT: (C)1980,JPO&Japio
JP9689578A 1978-08-08 1978-08-08 Manufacturing method of semiconductor integrated circuit device with lateral transistor Pending JPS5522875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9689578A JPS5522875A (en) 1978-08-08 1978-08-08 Manufacturing method of semiconductor integrated circuit device with lateral transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9689578A JPS5522875A (en) 1978-08-08 1978-08-08 Manufacturing method of semiconductor integrated circuit device with lateral transistor

Publications (1)

Publication Number Publication Date
JPS5522875A true JPS5522875A (en) 1980-02-18

Family

ID=14177102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9689578A Pending JPS5522875A (en) 1978-08-08 1978-08-08 Manufacturing method of semiconductor integrated circuit device with lateral transistor

Country Status (1)

Country Link
JP (1) JPS5522875A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135364B2 (en) 2001-04-25 2006-11-14 Sanken Electric Co., Ltd. Method of fabricating semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135364B2 (en) 2001-04-25 2006-11-14 Sanken Electric Co., Ltd. Method of fabricating semiconductor integrated circuit

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JPS5522875A (en) Manufacturing method of semiconductor integrated circuit device with lateral transistor