JPS55162244A - Forming method of metal wiring - Google Patents

Forming method of metal wiring

Info

Publication number
JPS55162244A
JPS55162244A JP6962679A JP6962679A JPS55162244A JP S55162244 A JPS55162244 A JP S55162244A JP 6962679 A JP6962679 A JP 6962679A JP 6962679 A JP6962679 A JP 6962679A JP S55162244 A JPS55162244 A JP S55162244A
Authority
JP
Japan
Prior art keywords
film
sputtering
metal wiring
pressure
torr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6962679A
Other languages
Japanese (ja)
Inventor
Katsuhiro Hirata
Shinichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6962679A priority Critical patent/JPS55162244A/en
Publication of JPS55162244A publication Critical patent/JPS55162244A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make the cross section taper slow when the patternizing is done later by the method wherein the pressure of an inert gas is gradually increased during the evaporation when metal film is evaporated by sputtering which is in contact with the substrate via the contact hole of oxide film coated on a semiconductor substrate. CONSTITUTION:Oxide film 2 is coated on the surface of semiconductor substrate 1, contact hole 2a is cut, and metal film 3, which is to become metal wiring, is formed on the entire surface by sputtering. At this time, the distance between the electrodes of the sputtering device and the power supply are made constant, and the pressure of Ar gas drawn inside is gradually increased. That is, the gas pressure is increased continuously or in steps, several m torr to 30m torr, form the start of sputtering to its completion. By this, the inside and the surface of film 3 assume different properties, and the particles of surface film 3b becom more coarse than those of film 3a in the neighborhood of substrate 1. Consequently, when etching is operated by placing a mask of photoresist film 4 on film 3b, the end part of the metal wiring remaining on hole 2a is made slow.
JP6962679A 1979-06-01 1979-06-01 Forming method of metal wiring Pending JPS55162244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6962679A JPS55162244A (en) 1979-06-01 1979-06-01 Forming method of metal wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6962679A JPS55162244A (en) 1979-06-01 1979-06-01 Forming method of metal wiring

Publications (1)

Publication Number Publication Date
JPS55162244A true JPS55162244A (en) 1980-12-17

Family

ID=13408255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6962679A Pending JPS55162244A (en) 1979-06-01 1979-06-01 Forming method of metal wiring

Country Status (1)

Country Link
JP (1) JPS55162244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
US6380058B2 (en) 1998-08-07 2002-04-30 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
US6380058B2 (en) 1998-08-07 2002-04-30 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
EP0020776A4 (en) Method of forming patterns.
JPS55162244A (en) Forming method of metal wiring
JPS52120782A (en) Manufacture of semiconductor device
JPS57157545A (en) Manufacture of semiconductor device
JPS52119172A (en) Forming method of fine pattern
JPS57145340A (en) Manufacture of semiconductor device
JPS5669843A (en) Manufacture of semiconductor device
JPS6413741A (en) Formation of tungsten structure
JPS5633891A (en) Light emitting semiconductor device
JPS56122143A (en) Manufacture of semiconductor device
JPS57155539A (en) Mask
JPS5650514A (en) Formation of fine pattern
JPS52124860A (en) Electrode formation method for semiconductor devices
JPS5666038A (en) Formation of micro-pattern
JPS5511167A (en) Dry etching method
JPS6441239A (en) Thin film manufacturing equipment and manufacture of metallic wiring thereby
JPS52124884A (en) Production of semiconductor device
JPS57106120A (en) Manufacture of semiconductor device
JPS56130925A (en) Manufacture of semiconductor device
JPS5368165A (en) Production of semiconductor device
JPS5772331A (en) Manufacture of semiconductor device
JPS5720450A (en) Forming method for pattern of semiconductor device
JPS5772350A (en) Fabrication of semiconductor device
JPS56101745A (en) Formation of microminiature electrode
JPS55166925A (en) Application of metal film on semiconductor substrate