JPS55162148A - Multiple rule type high speed multiplication system - Google Patents

Multiple rule type high speed multiplication system

Info

Publication number
JPS55162148A
JPS55162148A JP6749579A JP6749579A JPS55162148A JP S55162148 A JPS55162148 A JP S55162148A JP 6749579 A JP6749579 A JP 6749579A JP 6749579 A JP6749579 A JP 6749579A JP S55162148 A JPS55162148 A JP S55162148A
Authority
JP
Japan
Prior art keywords
order
low
product
bits
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6749579A
Other languages
English (en)
Other versions
JPS6042965B2 (ja
Inventor
Aisuke Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP54067495A priority Critical patent/JPS6042965B2/ja
Priority to US06/152,681 priority patent/US4346451A/en
Priority to DE3020767A priority patent/DE3020767C2/de
Priority to GB8017949A priority patent/GB2054221B/en
Publication of JPS55162148A publication Critical patent/JPS55162148A/ja
Publication of JPS6042965B2 publication Critical patent/JPS6042965B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
JP54067495A 1979-06-01 1979-06-01 複数法形高速乗算装置 Expired JPS6042965B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP54067495A JPS6042965B2 (ja) 1979-06-01 1979-06-01 複数法形高速乗算装置
US06/152,681 US4346451A (en) 1979-06-01 1980-05-23 Dual moduli exponent transform type high speed multiplication system
DE3020767A DE3020767C2 (de) 1979-06-01 1980-05-31 Schaltungsanordnung zur Restklassen-Multiplikation
GB8017949A GB2054221B (en) 1979-06-01 1980-06-02 Dual modulus multiplying system comprising a partial product calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54067495A JPS6042965B2 (ja) 1979-06-01 1979-06-01 複数法形高速乗算装置

Publications (2)

Publication Number Publication Date
JPS55162148A true JPS55162148A (en) 1980-12-17
JPS6042965B2 JPS6042965B2 (ja) 1985-09-26

Family

ID=13346621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54067495A Expired JPS6042965B2 (ja) 1979-06-01 1979-06-01 複数法形高速乗算装置

Country Status (4)

Country Link
US (1) US4346451A (ja)
JP (1) JPS6042965B2 (ja)
DE (1) DE3020767C2 (ja)
GB (1) GB2054221B (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3138698A1 (de) * 1981-09-29 1983-04-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zur potenzierung grosser binaerzahlen in einer restklasse modulo n, insbesondere zur verschluesselung und entschluesselung digital dargestellter nachrichten
US4965825A (en) 1981-11-03 1990-10-23 The Personalized Mass Media Corporation Signal processing apparatus and methods
US4506340A (en) * 1983-04-04 1985-03-19 Honeywell Information Systems Inc. Method and apparatus for producing the residue of the product of two residues
DE3587670T2 (de) * 1984-01-21 1994-06-23 Sony Corp Verfahren und schaltung zur dekodierung von fehlercode-daten.
US5144574A (en) * 1989-01-30 1992-09-01 Nippon Telegraph And Telephone Corporation Modular multiplication method and the system for processing data
US5073870A (en) * 1989-01-30 1991-12-17 Nippon Telegraph And Telephone Corporation Modular multiplication method and the system for processing data
US5446909A (en) * 1992-12-11 1995-08-29 National Semiconductor Corporation Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand
FR2705475B1 (fr) * 1993-05-19 1995-07-28 France Telecom Multiplieur exempt de débordement interne, notamment multiplieur bit-série, et procédé pour empêcher un débordement interne d'un multiplieur.
DE10107376A1 (de) * 2001-02-16 2002-08-29 Infineon Technologies Ag Verfahren und Vorrichtung zum modularen Multiplizieren und Rechenwerk zum modularen Multiplizieren
US7558817B2 (en) * 2002-04-29 2009-07-07 Infineon Technologies Ag Apparatus and method for calculating a result of a modular multiplication
DE10260660B3 (de) * 2002-12-23 2004-06-09 Infineon Technologies Ag Modulare Multiplikation mit paralleler Berechnung der Look-Ahead-Parameter u.a. bei der kryptographischen Berechnung
US7739323B2 (en) * 2006-06-20 2010-06-15 International Business Machines Corporation Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator
KR101326078B1 (ko) * 2007-10-11 2013-11-08 삼성전자주식회사 모듈러 곱셈 방법, 모듈러 곱셈기 및 모듈러 곱셈기를구비하는 암호 연산 시스템
CN102591615A (zh) * 2012-01-16 2012-07-18 中国人民解放军国防科学技术大学 结构化混合位宽乘法运算方法及装置
KR102645836B1 (ko) * 2021-11-12 2024-03-08 강창국 대기 시료 채취장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH412411A (de) * 1959-12-30 1966-04-30 Ibm Vorrichtung zur Durchführung von Multiplikationen und Divisionen im Zahlensystem der Restklassen
SU579618A1 (ru) * 1975-03-25 1977-11-05 Институт математики и механики АН Казахской ССР Устройство дл умножени
US4107783A (en) * 1977-02-02 1978-08-15 The Board Of Trustees Of The Leland Stanford Junior University System for processing arithmetic information using residue arithmetic

Also Published As

Publication number Publication date
DE3020767C2 (de) 1986-10-09
GB2054221B (en) 1983-06-02
JPS6042965B2 (ja) 1985-09-26
DE3020767A1 (de) 1980-12-04
US4346451A (en) 1982-08-24
GB2054221A (en) 1981-02-11

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