JPS55150253A - Manufacturing of composite hybrid integrated circuit - Google Patents
Manufacturing of composite hybrid integrated circuitInfo
- Publication number
- JPS55150253A JPS55150253A JP5726179A JP5726179A JPS55150253A JP S55150253 A JPS55150253 A JP S55150253A JP 5726179 A JP5726179 A JP 5726179A JP 5726179 A JP5726179 A JP 5726179A JP S55150253 A JPS55150253 A JP S55150253A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- lead wire
- integrated circuit
- film
- beam lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4822—Beam leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Recording Measured Values (AREA)
Abstract
PURPOSE:To obtain a projected beam lead wire by extending the external connection lead wire of a thin film integrated circuit on a spacer film formed at the end of a substrate, removing selectively the spacer film and removing the end of the substrate. CONSTITUTION:A glass layer 2 is formed on an alumina substrate 1, respective heaters 3, bonding layer 4, and a main conductive layer 5 are formed to a conductive lead wire 45, and a protective film 6 is formed thereon. A snap wire 11 is formed perpendicularly to the conductive lead wire 45 on the back surface of the substrate. A spacer film 7 and a beam lead conductor 8 are formed at the end of the conductive lead wire 45 by an ordinary thin film integrated circuit forming process. Subsequently, the film 7 is selectively removed to isolate the beam lead wire 8 from the surface of the substrate. Thereafter, when the substrate and the glass layer are destroyed along the snap line, the beam lead wire 8 is projected from the end of the substrate. In this manner, a high density integrated circuit with beam lead can be obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5726179A JPS55150253A (en) | 1979-05-10 | 1979-05-10 | Manufacturing of composite hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5726179A JPS55150253A (en) | 1979-05-10 | 1979-05-10 | Manufacturing of composite hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55150253A true JPS55150253A (en) | 1980-11-22 |
Family
ID=13050577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5726179A Pending JPS55150253A (en) | 1979-05-10 | 1979-05-10 | Manufacturing of composite hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55150253A (en) |
-
1979
- 1979-05-10 JP JP5726179A patent/JPS55150253A/en active Pending
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