JPS55146951A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS55146951A
JPS55146951A JP5348679A JP5348679A JPS55146951A JP S55146951 A JPS55146951 A JP S55146951A JP 5348679 A JP5348679 A JP 5348679A JP 5348679 A JP5348679 A JP 5348679A JP S55146951 A JPS55146951 A JP S55146951A
Authority
JP
Japan
Prior art keywords
framework
frame
lead
lead frame
connecting piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5348679A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6239543B2 (enExample
Inventor
Kazuo Shimizu
Fumihito Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5348679A priority Critical patent/JPS55146951A/ja
Publication of JPS55146951A publication Critical patent/JPS55146951A/ja
Publication of JPS6239543B2 publication Critical patent/JPS6239543B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP5348679A 1979-05-02 1979-05-02 Lead frame Granted JPS55146951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5348679A JPS55146951A (en) 1979-05-02 1979-05-02 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5348679A JPS55146951A (en) 1979-05-02 1979-05-02 Lead frame

Publications (2)

Publication Number Publication Date
JPS55146951A true JPS55146951A (en) 1980-11-15
JPS6239543B2 JPS6239543B2 (enExample) 1987-08-24

Family

ID=12944166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5348679A Granted JPS55146951A (en) 1979-05-02 1979-05-02 Lead frame

Country Status (1)

Country Link
JP (1) JPS55146951A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500340A (ja) * 1982-03-08 1984-03-01 モトロ−ラ・インコ−ポレ−テツド 集積回路のリ−ドフレ−ム
JPS59104149A (ja) * 1982-12-06 1984-06-15 Hitachi Chem Co Ltd 半導体類のパツケ−ジ成形方法
JPS59132640A (ja) * 1983-01-20 1984-07-30 Nec Corp 半導体素子用リ−ドフレ−ム
JPS60176552U (ja) * 1984-04-28 1985-11-22 凸版印刷株式会社 エツチング部品
JPS6139558A (ja) * 1984-07-31 1986-02-25 Toshiba Glass Co Ltd 半導体回路基板
JPH04164357A (ja) * 1990-10-29 1992-06-10 Nec Corp 半導体装置用リードフレーム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500340A (ja) * 1982-03-08 1984-03-01 モトロ−ラ・インコ−ポレ−テツド 集積回路のリ−ドフレ−ム
JPS59104149A (ja) * 1982-12-06 1984-06-15 Hitachi Chem Co Ltd 半導体類のパツケ−ジ成形方法
JPS59132640A (ja) * 1983-01-20 1984-07-30 Nec Corp 半導体素子用リ−ドフレ−ム
JPS60176552U (ja) * 1984-04-28 1985-11-22 凸版印刷株式会社 エツチング部品
JPS6139558A (ja) * 1984-07-31 1986-02-25 Toshiba Glass Co Ltd 半導体回路基板
JPH04164357A (ja) * 1990-10-29 1992-06-10 Nec Corp 半導体装置用リードフレーム

Also Published As

Publication number Publication date
JPS6239543B2 (enExample) 1987-08-24

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