JPS55138864A - Method of fabricating semiconductor assembling substrate - Google Patents

Method of fabricating semiconductor assembling substrate

Info

Publication number
JPS55138864A
JPS55138864A JP4711879A JP4711879A JPS55138864A JP S55138864 A JPS55138864 A JP S55138864A JP 4711879 A JP4711879 A JP 4711879A JP 4711879 A JP4711879 A JP 4711879A JP S55138864 A JPS55138864 A JP S55138864A
Authority
JP
Japan
Prior art keywords
electrode
opening
resist
forming
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4711879A
Other languages
English (en)
Inventor
Masao Hayakawa
Takamichi Maeda
Masao Kumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4711879A priority Critical patent/JPS55138864A/ja
Publication of JPS55138864A publication Critical patent/JPS55138864A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP4711879A 1979-04-16 1979-04-16 Method of fabricating semiconductor assembling substrate Pending JPS55138864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4711879A JPS55138864A (en) 1979-04-16 1979-04-16 Method of fabricating semiconductor assembling substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4711879A JPS55138864A (en) 1979-04-16 1979-04-16 Method of fabricating semiconductor assembling substrate

Publications (1)

Publication Number Publication Date
JPS55138864A true JPS55138864A (en) 1980-10-30

Family

ID=12766241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4711879A Pending JPS55138864A (en) 1979-04-16 1979-04-16 Method of fabricating semiconductor assembling substrate

Country Status (1)

Country Link
JP (1) JPS55138864A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141989A (en) * 1981-02-26 1982-09-02 Fujikura Ltd Flexible printed circuit board and method of producing same
JPS57204157A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS57204158A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS62200738A (ja) * 1986-02-28 1987-09-04 Seiko Epson Corp 回路基板構造
JPS62211930A (ja) * 1986-03-12 1987-09-17 Seiko Epson Corp 基板導体層への突起製造方法
JPS63129635A (ja) * 1986-11-20 1988-06-02 Seiko Epson Corp バンプ付基板
JPS63142660A (ja) * 1986-12-04 1988-06-15 Dainippon Screen Mfg Co Ltd リ−ドフレ−ムの製造方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141989A (en) * 1981-02-26 1982-09-02 Fujikura Ltd Flexible printed circuit board and method of producing same
JPS6367360B2 (ja) * 1981-02-26 1988-12-26 Fujikura Cable Works Ltd
JPS57204157A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS57204158A (en) * 1981-06-11 1982-12-14 Shindo Denshi Kogyo Kk Manufacture of wiring section for mounting chip
JPS62200738A (ja) * 1986-02-28 1987-09-04 Seiko Epson Corp 回路基板構造
JPH0533533B2 (ja) * 1986-02-28 1993-05-19 Seiko Epson Corp
JPS62211930A (ja) * 1986-03-12 1987-09-17 Seiko Epson Corp 基板導体層への突起製造方法
JPH0474865B2 (ja) * 1986-03-12 1992-11-27
JPS63129635A (ja) * 1986-11-20 1988-06-02 Seiko Epson Corp バンプ付基板
JPH0478175B2 (ja) * 1986-11-20 1992-12-10 Seiko Epson Corp
JPS63142660A (ja) * 1986-12-04 1988-06-15 Dainippon Screen Mfg Co Ltd リ−ドフレ−ムの製造方法
JPH0330298B2 (ja) * 1986-12-04 1991-04-26

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