JPS6489585A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPS6489585A
JPS6489585A JP24748287A JP24748287A JPS6489585A JP S6489585 A JPS6489585 A JP S6489585A JP 24748287 A JP24748287 A JP 24748287A JP 24748287 A JP24748287 A JP 24748287A JP S6489585 A JPS6489585 A JP S6489585A
Authority
JP
Japan
Prior art keywords
inner layer
layer patterns
continuity
layers
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24748287A
Other languages
Japanese (ja)
Inventor
Hiroo Tera
Kazuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP24748287A priority Critical patent/JPS6489585A/en
Publication of JPS6489585A publication Critical patent/JPS6489585A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To improve reliability without strict control of processing conditions, by bringing inner layer patterns formed on both faces of an insulating substrate in continuity through a throughhole piercing the substrate, coating the inner layer patterns with insulator in their partial exposure, and by forming an outer shield layer over this coating layer to be in continuity to the exposed part of inner layer patterns. CONSTITUTION:Inner layer patterns 2, 3 are formed on both faces of an insulating substrate 1, respectively. A through-hole 4 and a via hole 5 are formed through the insulating substrate 1 in the thickness direction, and the inner layer patterns 2, 3 are in continuity through the holes 4, 5. The inner layer patterns 2, 3 are coated with an insulating coating layers 7 with specified parts remaining as exposed parts 2a, 3a, 3c, and 3d. Conductive paste layers 8, 9 are printed on the insulating coating layer 7. After formation of these conductive paste layers 8, 9, exterior shield layers 10, 11 are formed out of copper films formed by electroless copper plating and in continuity to part of the inner layer patterns via exposed parts 2a, 3b.
JP24748287A 1987-09-30 1987-09-30 Multilayer wiring board Pending JPS6489585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24748287A JPS6489585A (en) 1987-09-30 1987-09-30 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24748287A JPS6489585A (en) 1987-09-30 1987-09-30 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPS6489585A true JPS6489585A (en) 1989-04-04

Family

ID=17164117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24748287A Pending JPS6489585A (en) 1987-09-30 1987-09-30 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS6489585A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02290092A (en) * 1989-02-21 1990-11-29 Tatsuta Electric Wire & Cable Co Ltd Printed wiring substrate
US5158657A (en) * 1990-03-22 1992-10-27 Canon Kabushiki Kaisha Circuit substrate and process for its production

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02290092A (en) * 1989-02-21 1990-11-29 Tatsuta Electric Wire & Cable Co Ltd Printed wiring substrate
US5158657A (en) * 1990-03-22 1992-10-27 Canon Kabushiki Kaisha Circuit substrate and process for its production

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